diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/bugpoint.cc | 18 | ||||
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 30 |
2 files changed, 41 insertions, 7 deletions
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index ad6a07fa0..a75927393 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -133,6 +133,7 @@ struct BugpointPass : public Pass { int index = 0; if (modules) { + Module *removed_module = nullptr; for (auto module : design_copy->modules()) { if (module->get_blackbox_attribute()) @@ -141,10 +142,14 @@ struct BugpointPass : public Pass { if (index++ == seed) { log("Trying to remove module %s.\n", module->name.c_str()); - design_copy->remove(module); - return design_copy; + removed_module = module; + break; } } + if (removed_module) { + design_copy->remove(removed_module); + return design_copy; + } } if (ports) { @@ -178,15 +183,20 @@ struct BugpointPass : public Pass { if (mod->get_blackbox_attribute()) continue; + Cell *removed_cell = nullptr; for (auto cell : mod->cells()) { if (index++ == seed) { log("Trying to remove cell %s.%s.\n", mod->name.c_str(), cell->name.c_str()); - mod->remove(cell); - return design_copy; + removed_cell = cell; + break; } } + if (removed_cell) { + mod->remove(removed_cell); + return design_copy; + } } } if (connections) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 3880b19fe..95d74d1eb 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -334,10 +334,16 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first)); } - for (auto ¶m : cell->parameters) - if (mod->avail_parameters.count(param.first) == 0 && param.first[0] != '$' && strchr(param.first.c_str(), '.') == NULL) + for (auto ¶m : cell->parameters) { + if (param.first[0] == '$' && '0' <= param.first[1] && param.first[1] <= '9') { + int id = atoi(param.first.c_str()+1); + if (id <= 0 || id > GetSize(mod->avail_parameters)) + log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d parameters, requested parameter %d.\n", + log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->avail_parameters), id); + } else if (mod->avail_parameters.count(param.first) == 0 && param.first[0] != '$' && strchr(param.first.c_str(), '.') == NULL) log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(param.first)); + } } } @@ -939,7 +945,8 @@ struct HierarchyPass : public Pass { for (auto mod : design->modules()) for (auto cell : mod->cells()) { - if (design->module(cell->type) == nullptr) + RTLIL::Module *cell_mod = design->module(cell->type); + if (cell_mod == nullptr) continue; for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { @@ -947,6 +954,23 @@ struct HierarchyPass : public Pass { pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod, cell)); break; } + + pool<std::pair<IdString, IdString>> params_rename; + for (const auto &p : cell->parameters) { + if (p.first[0] == '$' && '0' <= p.first[1] && p.first[1] <= '9') { + int id = atoi(p.first.c_str()+1); + if (id <= 0 || id > GetSize(cell_mod->avail_parameters)) { + log(" Failed to map positional parameter %d of cell %s.%s (%s).\n", + id, RTLIL::id2cstr(mod->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + } else { + params_rename.insert(std::make_pair(p.first, cell_mod->avail_parameters[id - 1])); + } + } + } + for (const auto &p : params_rename) { + cell->setParam(p.second, cell->getParam(p.first)); + cell->unsetParam(p.first); + } } for (auto module : pos_mods) |