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-rw-r--r--passes/cmds/Makefile.inc1
-rw-r--r--passes/cmds/logger.cc201
-rw-r--r--passes/cmds/show.cc19
-rw-r--r--passes/hierarchy/hierarchy.cc76
-rw-r--r--passes/opt/Makefile.inc1
-rw-r--r--passes/opt/opt_clean.cc18
-rw-r--r--passes/opt/opt_lut_ins.cc278
-rw-r--r--passes/opt/opt_merge.cc17
-rw-r--r--passes/pmgen/xilinx_dsp.cc7
-rw-r--r--passes/sat/clk2fflogic.cc83
-rw-r--r--passes/techmap/abc9.cc55
-rw-r--r--passes/techmap/abc9_exe.cc7
-rw-r--r--passes/techmap/abc9_ops.cc612
-rw-r--r--passes/techmap/extract_counter.cc451
-rw-r--r--passes/techmap/iopadmap.cc77
15 files changed, 1670 insertions, 233 deletions
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 07a5d3ddc..20b38bf8e 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -33,3 +33,4 @@ OBJS += passes/cmds/blackbox.o
OBJS += passes/cmds/ltp.o
OBJS += passes/cmds/bugpoint.o
OBJS += passes/cmds/scratchpad.o
+OBJS += passes/cmds/logger.o
diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc
new file mode 100644
index 000000000..bd1038a7e
--- /dev/null
+++ b/passes/cmds/logger.cc
@@ -0,0 +1,201 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 Miodrag Milanovic <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct LoggerPass : public Pass {
+ LoggerPass() : Pass("logger", "set logger properties") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" logger [options]\n");
+ log("\n");
+ log("This command sets global logger properties, also available using command line\n");
+ log("options.\n");
+ log("\n");
+ log(" -[no]time\n");
+ log(" enable/disable display of timestamp in log output.\n");
+ log("\n");
+ log(" -[no]stderr\n");
+ log(" enable/disable logging errors to stderr.\n");
+ log("\n");
+ log(" -warn regex\n");
+ log(" print a warning for all log messages matching the regex.\n");
+ log("\n");
+ log(" -nowarn regex\n");
+ log(" if a warning message matches the regex, it is printed as regular\n");
+ log(" message instead.\n");
+ log("\n");
+ log(" -werror regex\n");
+ log(" if a warning message matches the regex, it is printed as error\n");
+ log(" message instead and the tool terminates with a nonzero return code.\n");
+ log("\n");
+ log(" -[no]debug\n");
+ log(" globally enable/disable debug log messages.\n");
+ log("\n");
+ log(" -experimental <feature>\n");
+ log(" do not print warnings for the specified experimental feature\n");
+ log("\n");
+ log(" -expect <type> <regex> <expected_count>\n");
+ log(" expect log,warning or error to appear. In case of error return code is 0.\n");
+ log("\n");
+ log(" -expect-no-warnings\n");
+ log(" gives error in case there is at least one warning that is not expected.\n");
+ log("\n");
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design * design) YS_OVERRIDE
+ {
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+
+ if (args[argidx] == "-time") {
+ log_time = true;
+ log("Enabled timestamp in logs.\n");
+ continue;
+ }
+ if (args[argidx] == "-notime") {
+ log_time = false;
+ log("Disabled timestamp in logs.\n");
+ continue;
+ }
+ if (args[argidx] == "-stderr") {
+ log_error_stderr = true;
+ log("Enabled loggint errors to stderr.\n");
+ continue;
+ }
+ if (args[argidx] == "-nostderr") {
+ log_error_stderr = false;
+ log("Disabled loggint errors to stderr.\n");
+ continue;
+ }
+ if (args[argidx] == "-warn" && argidx+1 < args.size()) {
+ std::string pattern = args[++argidx];
+ if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
+ try {
+ log("Added regex '%s' for warnings to warn list.\n", pattern.c_str());
+ log_warn_regexes.push_back(std::regex(pattern,
+ std::regex_constants::nosubs |
+ std::regex_constants::optimize |
+ std::regex_constants::egrep));
+ }
+ catch (const std::regex_error& e) {
+ log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str());
+ }
+ continue;
+ }
+ if (args[argidx] == "-nowarn" && argidx+1 < args.size()) {
+ std::string pattern = args[++argidx];
+ if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
+ try {
+ log("Added regex '%s' for warnings to nowarn list.\n", pattern.c_str());
+ log_nowarn_regexes.push_back(std::regex(pattern,
+ std::regex_constants::nosubs |
+ std::regex_constants::optimize |
+ std::regex_constants::egrep));
+ }
+ catch (const std::regex_error& e) {
+ log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str());
+ }
+ continue;
+ }
+ if (args[argidx] == "-werror" && argidx+1 < args.size()) {
+ std::string pattern = args[++argidx];
+ if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
+ try {
+ log("Added regex '%s' for warnings to werror list.\n", pattern.c_str());
+ log_werror_regexes.push_back(std::regex(pattern,
+ std::regex_constants::nosubs |
+ std::regex_constants::optimize |
+ std::regex_constants::egrep));
+ }
+ catch (const std::regex_error& e) {
+ log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str());
+ }
+ continue;
+ }
+ if (args[argidx] == "-debug") {
+ log_force_debug = 1;
+ log("Enabled debug log messages.\n");
+ continue;
+ }
+ if (args[argidx] == "-nodebug") {
+ log_force_debug = 0;
+ log("Disabled debug log messages.\n");
+ continue;
+ }
+ if (args[argidx] == "-experimental" && argidx+1 < args.size()) {
+ std::string value = args[++argidx];
+ log("Added '%s' experimental ignore list.\n", value.c_str());
+ log_experimentals_ignored.insert(value);
+ continue;
+ }
+ if (args[argidx] == "-expect" && argidx+3 < args.size()) {
+ std::string type = args[++argidx];
+ if (type!="error" && type!="warning" && type!="log")
+ log_cmd_error("Expect command require type to be 'log', 'warning' or 'error' !\n");
+ if (type=="error" && log_expect_error.size()>0)
+ log_cmd_error("Only single error message can be expected !\n");
+ std::string pattern = args[++argidx];
+ if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
+ int count = atoi(args[++argidx].c_str());
+ if (count<=0)
+ log_cmd_error("Number of expected messages must be higher then 0 !\n");
+ if (type=="error" && count!=1)
+ log_cmd_error("Expected error message occurrences must be 1 !\n");
+ log("Added regex '%s' for warnings to expected %s list.\n", pattern.c_str(), type.c_str());
+ try {
+ if (type=="error")
+ log_expect_error.push_back(std::make_pair(std::regex(pattern,
+ std::regex_constants::nosubs |
+ std::regex_constants::optimize |
+ std::regex_constants::egrep), LogExpectedItem(pattern, count)));
+ else if (type=="warning")
+ log_expect_warning.push_back(std::make_pair(std::regex(pattern,
+ std::regex_constants::nosubs |
+ std::regex_constants::optimize |
+ std::regex_constants::egrep), LogExpectedItem(pattern, count)));
+ else
+ log_expect_log.push_back(std::make_pair(std::regex(pattern,
+ std::regex_constants::nosubs |
+ std::regex_constants::optimize |
+ std::regex_constants::egrep), LogExpectedItem(pattern, count)));
+ }
+ catch (const std::regex_error& e) {
+ log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str());
+ }
+ continue;
+ }
+ if (args[argidx] == "-expect-no-warnings") {
+ log_expect_no_warnings = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design, false);
+ }
+} LoggerPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index eeef24bde..e0d428811 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -668,6 +668,10 @@ struct ShowPass : public Pass {
log(" -notitle\n");
log(" do not add the module name as graph title to the dot file\n");
log("\n");
+ log(" -nobg\n");
+ log(" don't run viewer in the background, IE wait for the viewer tool to\n");
+ log(" exit before returning\n");
+ log("\n");
log("When no <format> is specified, 'dot' is used. When no <format> and <viewer> is\n");
log("specified, 'xdot' is used to display the schematic (POSIX systems only).\n");
log("\n");
@@ -706,6 +710,7 @@ struct ShowPass : public Pass {
bool flag_abbreviate = true;
bool flag_notitle = false;
bool custom_prefix = false;
+ std::string background = "&";
RTLIL::IdString colorattr;
size_t argidx;
@@ -787,6 +792,10 @@ struct ShowPass : public Pass {
flag_notitle = true;
continue;
}
+ if (arg == "-nobg") {
+ background= "";
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -859,21 +868,19 @@ struct ShowPass : public Pass {
// system()/cmd.exe does not understand single quotes nor
// background tasks on Windows. So we have to pause yosys
// until the viewer exits.
- #define VIEW_CMD "%s \"%s\""
+ std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str());
#else
- #define VIEW_CMD "%s '%s' &"
+ std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str());
#endif
- std::string cmd = stringf(VIEW_CMD, viewer_exe.c_str(), out_file.c_str());
- #undef VIEW_CMD
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
} else
if (format.empty()) {
#ifdef __APPLE__
- std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' &", getuid(), dot_file.c_str(), dot_file.c_str());
+ std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str());
#else
- std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' &", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str());
+ std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str());
#endif
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index d8a628448..fa4a8ea29 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -548,6 +548,19 @@ RTLIL::Module *check_if_top_has_changed(Design *design, Module *top_mod)
return NULL;
}
+// Find a matching wire for an implicit port connection; traversing generate block scope
+RTLIL::Wire *find_implicit_port_wire(Module *module, Cell *cell, const std::string& port)
+{
+ const std::string &cellname = cell->name.str();
+ size_t idx = cellname.size();
+ while ((idx = cellname.find_last_of('.', idx-1)) != std::string::npos) {
+ Wire *found = module->wire(cellname.substr(0, idx+1) + port.substr(1));
+ if (found != nullptr)
+ return found;
+ }
+ return module->wire(port);
+}
+
struct HierarchyPass : public Pass {
HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
void help() YS_OVERRIDE
@@ -970,15 +983,71 @@ struct HierarchyPass : public Pass {
}
}
+ // Determine default values
+ dict<IdString, dict<IdString, Const>> defaults_db;
if (!nodefaults)
{
- dict<IdString, dict<IdString, Const>> defaults_db;
-
for (auto module : design->modules())
for (auto wire : module->wires())
if (wire->port_input && wire->attributes.count("\\defaultvalue"))
defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue");
+ }
+ // Process SV implicit wildcard port connections
+ std::set<Module*> blackbox_derivatives;
+ std::vector<Module*> design_modules = design->modules();
+ for (auto module : design_modules)
+ {
+ for (auto cell : module->cells())
+ {
+ if (!cell->get_bool_attribute(ID(wildcard_port_conns)))
+ continue;
+ Module *m = design->module(cell->type);
+
+ if (m == nullptr)
+ log_error("Cell %s.%s (%s) has implicit port connections but the module it instantiates is unknown.\n",
+ RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
+
+ // Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
+ if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) {
+ IdString new_m_name = m->derive(design, cell->parameters, true);
+ if (new_m_name.empty())
+ continue;
+ if (new_m_name != m->name) {
+ m = design->module(new_m_name);
+ blackbox_derivatives.insert(m);
+ }
+ }
+
+ auto old_connections = cell->connections();
+ for (auto wire : m->wires()) {
+ // Find ports of the module that aren't explicitly connected
+ if (!wire->port_input && !wire->port_output)
+ continue;
+ if (old_connections.count(wire->name))
+ continue;
+ // Make sure a wire of correct name exists in the parent
+ Wire* parent_wire = find_implicit_port_wire(module, cell, wire->name.str());
+
+ // Missing wires are OK when a default value is set
+ if (!nodefaults && parent_wire == nullptr && defaults_db.count(cell->type) && defaults_db.at(cell->type).count(wire->name))
+ continue;
+
+ if (parent_wire == nullptr)
+ log_error("No matching wire for implicit port connection `%s' of cell %s.%s (%s).\n",
+ RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
+ if (parent_wire->width != wire->width)
+ log_error("Width mismatch between wire (%d bits) and port (%d bits) for implicit port connection `%s' of cell %s.%s (%s).\n",
+ parent_wire->width, wire->width,
+ RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
+ cell->setPort(wire->name, parent_wire);
+ }
+ cell->attributes.erase(ID(wildcard_port_conns));
+ }
+ }
+
+ if (!nodefaults)
+ {
for (auto module : design->modules())
for (auto cell : module->cells())
{
@@ -1000,9 +1069,6 @@ struct HierarchyPass : public Pass {
}
}
- std::set<Module*> blackbox_derivatives;
- std::vector<Module*> design_modules = design->modules();
-
for (auto module : design_modules)
{
pool<Wire*> wand_wor_index;
diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc
index 002c1a6a1..3133927bb 100644
--- a/passes/opt/Makefile.inc
+++ b/passes/opt/Makefile.inc
@@ -15,6 +15,7 @@ OBJS += passes/opt/wreduce.o
OBJS += passes/opt/opt_demorgan.o
OBJS += passes/opt/rmports.o
OBJS += passes/opt/opt_lut.o
+OBJS += passes/opt/opt_lut_ins.o
OBJS += passes/opt/pmux2shiftx.o
OBJS += passes/opt/muxpack.o
endif
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 2f69b3d4c..cac265a52 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -53,18 +53,24 @@ struct keep_cache_t
cache[module] = true;
if (!module->get_bool_attribute(ID::keep)) {
- bool found_keep = false;
- for (auto cell : module->cells())
- if (query(cell)) found_keep = true;
- cache[module] = found_keep;
+ bool found_keep = false;
+ for (auto cell : module->cells())
+ if (query(cell, true /* ignore_specify */)) {
+ found_keep = true;
+ break;
+ }
+ cache[module] = found_keep;
}
return cache[module];
}
- bool query(Cell *cell)
+ bool query(Cell *cell, bool ignore_specify = false)
{
- if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($specify2), ID($specify3), ID($specrule)))
+ if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
+ return true;
+
+ if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
return true;
if (cell->has_keep_attr())
diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc
new file mode 100644
index 000000000..cf5248ced
--- /dev/null
+++ b/passes/opt/opt_lut_ins.cc
@@ -0,0 +1,278 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct OptLutInsPass : public Pass {
+ OptLutInsPass() : Pass("opt_lut_ins", "discard unused LUT inputs") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" opt_lut_ins [options] [selection]\n");
+ log("\n");
+ log("This pass removes unused inputs from LUT cells (that is, inputs that can not\n");
+ log("influence the output signal given this LUT's value). While such LUTs cannot\n");
+ log("be directly emitted by ABC, they can be a result of various post-ABC\n");
+ log("transformations, such as mapping wide LUTs (not all sub-LUTs will use the\n");
+ log("full set of inputs) or optimizations such as xilinx_dffopt.\n");
+ log("\n");
+ log(" -tech <technology>\n");
+ log(" Instead of generic $lut cells, operate on LUT cells specific\n");
+ log(" to the given technology. Valid values are: xilinx, ecp5, gowin.\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing OPT_LUT_INS pass (discard unused LUT inputs).\n");
+ string techname;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-tech" && argidx+1 < args.size()) {
+ techname = args[++argidx];
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (techname != "" && techname != "xilinx" && techname != "ecp5" && techname != "gowin")
+ log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
+
+ for (auto module : design->selected_modules())
+ {
+ log("Optimizing LUTs in %s.\n", log_id(module));
+
+ std::vector<Cell *> remove_cells;
+ // Gather LUTs.
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->get_bool_attribute(ID::keep))
+ continue;
+ Const lut;
+ std::vector<SigBit> inputs;
+ std::vector<SigBit> output;
+ bool ignore_const = false;
+ if (techname == "") {
+ if (cell->type != ID($lut))
+ continue;
+ inputs = cell->getPort(ID::A).bits();
+ output = cell->getPort(ID::Y);
+ lut = cell->getParam(ID(LUT));
+ } else if (techname == "xilinx" || techname == "gowin") {
+ if (cell->type == ID(LUT1)) {
+ inputs = {
+ cell->getPort(ID(I0)),
+ };
+ } else if (cell->type == ID(LUT2)) {
+ inputs = {
+ cell->getPort(ID(I0)),
+ cell->getPort(ID(I1)),
+ };
+ } else if (cell->type == ID(LUT3)) {
+ inputs = {
+ cell->getPort(ID(I0)),
+ cell->getPort(ID(I1)),
+ cell->getPort(ID(I2)),
+ };
+ } else if (cell->type == ID(LUT4)) {
+ inputs = {
+ cell->getPort(ID(I0)),
+ cell->getPort(ID(I1)),
+ cell->getPort(ID(I2)),
+ cell->getPort(ID(I3)),
+ };
+ } else if (cell->type == ID(LUT5)) {
+ inputs = {
+ cell->getPort(ID(I0)),
+ cell->getPort(ID(I1)),
+ cell->getPort(ID(I2)),
+ cell->getPort(ID(I3)),
+ cell->getPort(ID(I4)),
+ };
+ } else if (cell->type == ID(LUT6)) {
+ inputs = {
+ cell->getPort(ID(I0)),
+ cell->getPort(ID(I1)),
+ cell->getPort(ID(I2)),
+ cell->getPort(ID(I3)),
+ cell->getPort(ID(I4)),
+ cell->getPort(ID(I5)),
+ };
+ } else {
+ // Not a LUT.
+ continue;
+ }
+ lut = cell->getParam(ID(INIT));
+ if (techname == "xilinx")
+ output = cell->getPort(ID(O));
+ else
+ output = cell->getPort(ID(F));
+ } else if (techname == "ecp5") {
+ if (cell->type == ID(LUT4)) {
+ inputs = {
+ cell->getPort(ID::A),
+ cell->getPort(ID::B),
+ cell->getPort(ID(C)),
+ cell->getPort(ID(D)),
+ };
+ lut = cell->getParam(ID(INIT));
+ output = cell->getPort(ID(Z));
+ ignore_const = true;
+ } else {
+ // Not a LUT.
+ continue;
+ }
+ }
+ std::vector<int> swizzle;
+ std::vector<SigBit> new_inputs;
+ bool doit = false;
+ for (int i = 0; i < GetSize(inputs); i++) {
+ SigBit input = inputs[i];
+ if (!input.wire) {
+ if (input.data == State::S1)
+ swizzle.push_back(-2);
+ else
+ swizzle.push_back(-1);
+ // For ECP5, smaller LUTs are
+ // implemented as LUT4s with
+ // extra const inputs. Do not
+ // consider that to be a reason
+ // to redo a LUT.
+ if (!ignore_const)
+ doit = true;
+ } else {
+ bool redundant = true;
+ for (int j = 0; j < GetSize(lut); j++) {
+ if (lut[j] != lut[j ^ 1 << i])
+ redundant = false;
+ }
+ if (redundant) {
+ swizzle.push_back(-1);
+ doit = true;
+ } else {
+ swizzle.push_back(GetSize(new_inputs));
+ new_inputs.push_back(input);
+ }
+ }
+ }
+ if (!doit)
+ continue;
+ log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs));
+ if (techname == "ecp5") {
+ // Pad the LUT to 4 inputs, adding consts from the front.
+ int extra = 4 - GetSize(new_inputs);
+ log_assert(extra >= 0);
+ if (extra) {
+ for (int i = 0; i < extra; i++)
+ new_inputs.insert(new_inputs.begin(), State::S0);
+ for (auto &swz : swizzle)
+ if (swz >= 0)
+ swz += extra;
+ }
+ }
+ Const new_lut(0, 1 << GetSize(new_inputs));
+ for (int i = 0; i < GetSize(new_lut); i++) {
+ int lidx = 0;
+ for (int j = 0; j < GetSize(inputs); j++) {
+ int val;
+ if (swizzle[j] == -2) {
+ val = 1;
+ } else if (swizzle[j] == -1) {
+ val = 0;
+ } else {
+ val = (i >> swizzle[j]) & 1;
+ }
+ lidx |= val << j;
+ }
+ new_lut[i] = lut[lidx];
+ }
+ // For ecp5, do not replace with a const driver — the nextpnr
+ // packer requires a complete set of LUTs for wide LUT muxes.
+ if (new_inputs.empty() && techname != "ecp5") {
+ // const driver.
+ remove_cells.push_back(cell);
+ module->connect(output, new_lut[0]);
+ } else {
+ if (techname == "") {
+ cell->setParam(ID(LUT), new_lut);
+ cell->setParam(ID(WIDTH), GetSize(new_inputs));
+ cell->setPort(ID::A, new_inputs);
+ } else if (techname == "ecp5") {
+ log_assert(GetSize(new_inputs) == 4);
+ cell->setParam(ID(INIT), new_lut);
+ cell->setPort(ID::A, new_inputs[0]);
+ cell->setPort(ID::B, new_inputs[1]);
+ cell->setPort(ID(C), new_inputs[2]);
+ cell->setPort(ID(D), new_inputs[3]);
+ } else {
+ // xilinx, gowin
+ cell->setParam(ID(INIT), new_lut);
+ if (techname == "xilinx")
+ log_assert(GetSize(new_inputs) <= 6);
+ else
+ log_assert(GetSize(new_inputs) <= 4);
+ if (GetSize(new_inputs) == 1)
+ cell->type = ID(LUT1);
+ else if (GetSize(new_inputs) == 2)
+ cell->type = ID(LUT2);
+ else if (GetSize(new_inputs) == 3)
+ cell->type = ID(LUT3);
+ else if (GetSize(new_inputs) == 4)
+ cell->type = ID(LUT4);
+ else if (GetSize(new_inputs) == 5)
+ cell->type = ID(LUT5);
+ else if (GetSize(new_inputs) == 6)
+ cell->type = ID(LUT6);
+ else
+ log_assert(0);
+ cell->unsetPort(ID(I0));
+ cell->unsetPort(ID(I1));
+ cell->unsetPort(ID(I2));
+ cell->unsetPort(ID(I3));
+ cell->unsetPort(ID(I4));
+ cell->unsetPort(ID(I5));
+ cell->setPort(ID(I0), new_inputs[0]);
+ if (GetSize(new_inputs) >= 2)
+ cell->setPort(ID(I1), new_inputs[1]);
+ if (GetSize(new_inputs) >= 3)
+ cell->setPort(ID(I2), new_inputs[2]);
+ if (GetSize(new_inputs) >= 4)
+ cell->setPort(ID(I3), new_inputs[3]);
+ if (GetSize(new_inputs) >= 5)
+ cell->setPort(ID(I4), new_inputs[4]);
+ if (GetSize(new_inputs) >= 6)
+ cell->setPort(ID(I5), new_inputs[5]);
+ }
+ }
+ }
+ for (auto cell : remove_cells)
+ module->remove(cell);
+ }
+ }
+} XilinxDffOptPass;
+
+PRIVATE_NAMESPACE_END
+
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index aaea6159e..8823a9061 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -222,7 +222,9 @@ struct OptMergeWorker
return true;
}
- if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) {
+ if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
+ cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
+ cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
for (size_t i = 0; i < q1.size(); i++)
@@ -323,6 +325,19 @@ struct OptMergeWorker
log_signal(it.second), log_signal(other_sig));
module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig);
+
+ if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+ cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
+ cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+ for (auto c : it.second.chunks()) {
+ auto jt = c.wire->attributes.find(ID(init));
+ if (jt == c.wire->attributes.end())
+ continue;
+ for (int i = c.offset; i < c.offset + c.width; i++)
+ jt->second[i] = State::Sx;
+ }
+ dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
+ }
}
}
log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 81c3c57c4..ae7967d7c 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -767,6 +767,9 @@ struct XilinxDspPass : public Pass {
log("to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series\n");
log("device.\n");
log("\n");
+ log("This pass is a no-op if the scratchpad variable 'xilinx_dsp.multonly' is set\n");
+ log("to 1.\n");
+ log("\n");
log("\n");
log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");
log("'(* use_dsp=\"simd\" *)' attribute attached to the output wire or attached to\n");
@@ -805,6 +808,10 @@ struct XilinxDspPass : public Pass {
family = "xcu";
for (auto module : design->selected_modules()) {
+
+ if (design->scratchpad_get_bool("xilinx_dsp.multonly"))
+ continue;
+
// Experimental feature: pack $add/$sub cells with
// (* use_dsp48="simd" *) into DSP48E1's using its
// SIMD feature
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index 4bb4aa047..f9e7783a9 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -214,14 +214,38 @@ struct Clk2fflogicPass : public Pass {
continue;
}
- if (cell->type.in("$dff", "$adff", "$dffsr"))
+ bool word_dff = cell->type.in("$dff", "$adff", "$dffsr");
+ if (word_dff || cell->type.in(ID($_DFF_N_), ID($_DFF_P_),
+ ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_),
+ ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
+ ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
{
- bool clkpol = cell->parameters["\\CLK_POLARITY"].as_bool();
+ bool clkpol;
+ SigSpec clk;
+ if (word_dff) {
+ clkpol = cell->parameters["\\CLK_POLARITY"].as_bool();
+ clk = cell->getPort("\\CLK");
+ }
+ else {
+ if (cell->type.in(ID($_DFF_P_), ID($_DFF_N_),
+ ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_)))
+ clkpol = cell->type[6] == 'P';
+ else if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
+ ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
+ clkpol = cell->type[8] == 'P';
+ else log_abort();
+ clk = cell->getPort("\\C");
+ }
- SigSpec clk = cell->getPort("\\CLK");
Wire *past_clk = module->addWire(NEW_ID);
past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
- module->addFf(NEW_ID, clk, past_clk);
+
+ if (word_dff)
+ module->addFf(NEW_ID, clk, past_clk);
+ else
+ module->addFfGate(NEW_ID, clk, past_clk);
SigSpec sig_d = cell->getPort("\\D");
SigSpec sig_q = cell->getPort("\\Q");
@@ -244,8 +268,14 @@ struct Clk2fflogicPass : public Pass {
Wire *past_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
- module->addFf(NEW_ID, sig_d, past_d);
- module->addFf(NEW_ID, sig_q, past_q);
+ if (word_dff) {
+ module->addFf(NEW_ID, sig_d, past_d);
+ module->addFf(NEW_ID, sig_q, past_q);
+ }
+ else {
+ module->addFfGate(NEW_ID, sig_d, past_d);
+ module->addFfGate(NEW_ID, sig_q, past_q);
+ }
if (cell->type == "$adff")
{
@@ -266,6 +296,26 @@ struct Clk2fflogicPass : public Pass {
module->addMux(NEW_ID, rstval, qval, arst, sig_q);
}
else
+ if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_)))
+ {
+ SigSpec arst = cell->getPort("\\R");
+ SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
+ SigBit rstval = (cell->type[8] == '1');
+
+ Wire *past_arst = module->addWire(NEW_ID);
+ module->addFfGate(NEW_ID, arst, past_arst);
+ if (cell->type[7] == 'P')
+ arst = module->OrGate(NEW_ID, arst, past_arst);
+ else
+ arst = module->AndGate(NEW_ID, arst, past_arst);
+
+ if (cell->type[7] == 'P')
+ module->addMuxGate(NEW_ID, qval, rstval, arst, sig_q);
+ else
+ module->addMuxGate(NEW_ID, rstval, qval, arst, sig_q);
+ }
+ else
if (cell->type == "$dffsr")
{
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
@@ -282,9 +332,30 @@ struct Clk2fflogicPass : public Pass {
module->addAnd(NEW_ID, qval, clrval, sig_q);
}
else
+ if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
+ ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
+ {
+ SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
+ SigSpec setval = cell->getPort("\\S");
+ SigSpec clrval = cell->getPort("\\R");
+
+ if (cell->type[9] != 'P')
+ setval = module->Not(NEW_ID, setval);
+
+ if (cell->type[10] == 'P')
+ clrval = module->Not(NEW_ID, clrval);
+
+ qval = module->OrGate(NEW_ID, qval, setval);
+ module->addAndGate(NEW_ID, qval, clrval, sig_q);
+ }
+ else if (cell->type == "$dff")
{
module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
}
+ else
+ {
+ module->addMuxGate(NEW_ID, past_q, past_d, clock_edge, sig_q);
+ }
Const initval;
bool assign_initval = false;
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2aeda16d6..5e650230d 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -145,6 +145,11 @@ struct Abc9Pass : public ScriptPass
log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
log(" 2, 3, .. inputs.\n");
log("\n");
+ log(" -maxlut <width>\n");
+ log(" when auto-generating the lut library, discard all luts equal to or\n");
+ log(" greater than this size (applicable when neither -lut nor -luts is\n");
+ log(" specified).\n");
+ log("\n");
log(" -dff\n");
log(" also pass $_ABC9_FF_ cells through to ABC. modules with many clock\n");
log(" domains are marked as such and automatically partitioned by ABC.\n");
@@ -175,6 +180,9 @@ struct Abc9Pass : public ScriptPass
std::stringstream exe_cmd;
bool dff_mode, cleanup;
+ bool lut_mode;
+ int maxlut;
+ std::string box_file;
void clear_flags() YS_OVERRIDE
{
@@ -182,6 +190,9 @@ struct Abc9Pass : public ScriptPass
exe_cmd << "abc9_exe";
dff_mode = false;
cleanup = true;
+ lut_mode = false;
+ maxlut = 0;
+ box_file = "";
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -202,9 +213,11 @@ struct Abc9Pass : public ScriptPass
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
if ((arg == "-exe" || arg == "-script" || arg == "-D" ||
- /* arg == "-S" || */ arg == "-lut" || arg == "-luts" ||
- arg == "-box" || arg == "-W") &&
+ /*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" ||
+ /*arg == "-box" ||*/ arg == "-W") &&
argidx+1 < args.size()) {
+ if (arg == "-lut" || arg == "-luts")
+ lut_mode = true;
exe_cmd << " " << arg << " " << args[++argidx];
continue;
}
@@ -222,6 +235,14 @@ struct Abc9Pass : public ScriptPass
cleanup = false;
continue;
}
+ if (arg == "-box" && argidx+1 < args.size()) {
+ box_file = args[++argidx];
+ continue;
+ }
+ if (arg == "-maxlut" && argidx+1 < args.size()) {
+ maxlut = atoi(args[++argidx].c_str());
+ continue;
+ }
if (arg == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
@@ -234,6 +255,9 @@ struct Abc9Pass : public ScriptPass
}
extra_args(args, argidx, design);
+ if (maxlut && lut_mode)
+ log_cmd_error("abc9 '-maxlut' option only applicable without '-lut' nor '-luts'.\n");
+
log_assert(design);
if (design->selected_modules().empty()) {
log_warning("No modules selected for ABC9 techmapping.\n");
@@ -251,11 +275,20 @@ struct Abc9Pass : public ScriptPass
void script() YS_OVERRIDE
{
if (check_label("pre")) {
+ run("abc9_ops -check");
run("scc -set_attr abc9_scc_id {}");
if (help_mode)
- run("abc9_ops -mark_scc -prep_xaiger [-dff]", "(option for -dff)");
+ run("abc9_ops -mark_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)");
else
- run("abc9_ops -mark_scc -prep_xaiger" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
+ run("abc9_ops -mark_scc -prep_delays -prep_xaiger" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
+ if (help_mode)
+ run("abc9_ops -prep_lut <maxlut>", "(skip if -lut or -luts)");
+ else if (!lut_mode)
+ run(stringf("abc9_ops -prep_lut %d", maxlut));
+ if (help_mode)
+ run("abc9_ops -prep_box [-dff]", "(skip if -box)");
+ else if (box_file.empty())
+ run(stringf("abc9_ops -prep_box %s", dff_mode ? "-dff" : ""));
run("select -set abc9_holes A:abc9_holes");
run("flatten -wb @abc9_holes");
run("techmap @abc9_holes");
@@ -269,8 +302,10 @@ struct Abc9Pass : public ScriptPass
if (check_label("map")) {
if (help_mode) {
run("foreach module in selection");
+ run(" abc9_ops -write_lut <abc-temp-dir>/input.lut", "(skip if '-lut' or '-luts')");
+ run(" abc9_ops -write_box <abc-temp-dir>/input.box");
run(" write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
- run(" abc9_exe -cwd <abc-temp-dir> [options]");
+ run(" abc9_exe [options] -cwd <abc-temp-dir> [-lut <abc-temp-dir>/input.lut] -box <abc-temp-dir>/input.box");
run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
run(" abc9_ops -reintegrate");
}
@@ -296,6 +331,9 @@ struct Abc9Pass : public ScriptPass
tempdir_name[0] = tempdir_name[4] = '_';
tempdir_name = make_temp_dir(tempdir_name);
+ if (!lut_mode)
+ run(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str()));
+ run(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str()));
run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
@@ -307,7 +345,12 @@ struct Abc9Pass : public ScriptPass
active_design->scratchpad_get_int("write_xaiger.num_inputs"),
num_outputs);
if (num_outputs) {
- run(stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str()));
+ std::string abc9_exe_cmd;
+ abc9_exe_cmd += stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str());
+ if (!lut_mode)
+ abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name.c_str());
+ abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str());
+ run(abc9_exe_cmd);
run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str()));
run("abc9_ops -reintegrate");
}
diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc
index 01bf46539..898285c69 100644
--- a/passes/techmap/abc9_exe.cc
+++ b/passes/techmap/abc9_exe.cc
@@ -362,7 +362,7 @@ struct Abc9ExePass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
- log_header(design, "Executing ABC9_MAP pass (technology mapping using ABC9).\n");
+ log_header(design, "Executing ABC9_EXE pass (technology mapping using ABC9).\n");
#ifdef ABCEXTERNAL
std::string exe_file = ABCEXTERNAL;
@@ -471,7 +471,7 @@ struct Abc9ExePass : public Pass {
// handle -lut / -luts args
if (!lut_arg.empty()) {
string arg = lut_arg;
- if (arg.find_first_not_of("0123456789:") == std::string::npos) {
+ if (arg.find_first_not_of("0123456789:,") == std::string::npos) {
size_t pos = arg.find_first_of(':');
int lut_mode = 0, lut_mode2 = 0;
if (pos != string::npos) {
@@ -510,9 +510,8 @@ struct Abc9ExePass : public Pass {
}
}
- // ABC expects a box file for XAIG
if (box_file.empty())
- box_file = "+/dummy.box";
+ log_cmd_error("abc9_exe '-box' option is mandatory.\n");
rewrite_filename(box_file);
if (!box_file.empty() && !is_absolute_path(box_file) && box_file[0] != '+')
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 9ad29a8f6..b0bd81698 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -22,6 +22,7 @@
#include "kernel/sigtools.h"
#include "kernel/utils.h"
#include "kernel/celltypes.h"
+#include "kernel/timinginfo.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@@ -33,6 +34,62 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
}
+void check(RTLIL::Design *design)
+{
+ dict<IdString,IdString> box_lookup;
+ for (auto m : design->modules()) {
+ if (m->name.begins_with("$paramod"))
+ continue;
+
+ auto flop = m->get_bool_attribute(ID(abc9_flop));
+ auto it = m->attributes.find(ID(abc9_box_id));
+ if (!flop) {
+ if (it == m->attributes.end())
+ continue;
+ auto id = it->second.as_int();
+ auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
+ if (!r.second)
+ log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
+ log_id(m), id, log_id(r.first->second));
+ }
+
+ // Make carry in the last PI, and carry out the last PO
+ // since ABC requires it this way
+ IdString carry_in, carry_out;
+ for (const auto &port_name : m->ports) {
+ auto w = m->wire(port_name);
+ log_assert(w);
+ if (w->get_bool_attribute("\\abc9_carry")) {
+ if (w->port_input) {
+ if (carry_in != IdString())
+ log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
+ carry_in = port_name;
+ }
+ if (w->port_output) {
+ if (carry_out != IdString())
+ log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", log_id(m));
+ carry_out = port_name;
+ }
+ }
+ }
+
+ if (carry_in != IdString() && carry_out == IdString())
+ log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", log_id(m));
+ if (carry_in == IdString() && carry_out != IdString())
+ log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", log_id(m));
+
+ if (flop) {
+ int num_outputs = 0;
+ for (auto port_name : m->ports) {
+ auto wire = m->wire(port_name);
+ if (wire->port_output) num_outputs++;
+ }
+ if (num_outputs != 1)
+ log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
+ }
+ }
+}
+
void mark_scc(RTLIL::Module *module)
{
// For every unique SCC found, (arbitrarily) find the first
@@ -85,20 +142,9 @@ void prep_dff(RTLIL::Module *module)
clkdomain_t key(abc9_clock);
auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
- auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
- log_assert(r2.second);
-
- Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
- if (abc9_init_wire == NULL)
- log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
- log_assert(GetSize(abc9_init_wire) == 1);
- SigSpec abc9_init = assign_map(abc9_init_wire);
- if (!abc9_init.is_fully_const())
- log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
- if (abc9_init == State::S1)
- log_error("'%s.init' in module '%s' has value 1'b1 which is not supported by 'abc9 -dff'.\n", cell->name.c_str(), log_id(module));
- r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
+ auto r2 = cell->attributes.insert(ID(abc9_mergeability));;
log_assert(r2.second);
+ r2.first->second = r.first->second;
}
RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
@@ -169,13 +215,11 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
continue;
auto inst_module = module->design->module(cell->type);
- bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");
- bool abc9_flop = false;
- if (abc9_box) {
- abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
- if (abc9_flop && !dff)
- continue;
+ bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
+ if (abc9_flop && !dff)
+ continue;
+ if ((inst_module && inst_module->get_bool_attribute("\\abc9_box")) || abc9_flop) {
auto r = box_ports.insert(cell->type);
if (r.second) {
// Make carry in the last PI, and carry out the last PO
@@ -185,25 +229,15 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
auto w = inst_module->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
- if (w->port_input) {
- if (carry_in != IdString())
- log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(inst_module));
+ log_assert(w->port_input != w->port_output);
+ if (w->port_input)
carry_in = port_name;
- }
- if (w->port_output) {
- if (carry_out != IdString())
- log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(inst_module));
+ else if (w->port_output)
carry_out = port_name;
- }
}
else
r.first->second.push_back(port_name);
}
-
- if (carry_in != IdString() && carry_out == IdString())
- log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(inst_module));
- if (carry_in == IdString() && carry_out != IdString())
- log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(inst_module));
if (carry_in != IdString()) {
r.first->second.push_back(carry_in);
r.first->second.push_back(carry_out);
@@ -232,8 +266,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto &it : bit_users)
if (bit_drivers.count(it.first))
for (auto driver_cell : bit_drivers.at(it.first))
- for (auto user_cell : it.second)
- toposort.edge(driver_cell, user_cell);
+ for (auto user_cell : it.second)
+ toposort.edge(driver_cell, user_cell);
if (ys_debug(1))
toposort.analyze_loops = true;
@@ -259,6 +293,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
holes_module->set_bool_attribute("\\abc9_holes");
dict<IdString, Cell*> cell_cache;
+ TimingInfo timing;
int port_id = 1, box_count = 0;
for (auto cell_name : toposort.sorted) {
@@ -266,22 +301,25 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type);
- if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
+ if (!box_module || (!box_module->get_bool_attribute("\\abc9_box") && !box_module->get_bool_attribute("\\abc9_flop")))
continue;
cell->attributes["\\abc9_box_seq"] = box_count++;
- IdString derived_name = box_module->derive(design, cell->parameters);
- box_module = design->module(derived_name);
+ IdString derived_type = box_module->derive(design, cell->parameters);
+ box_module = design->module(derived_type);
- auto r = cell_cache.insert(derived_name);
+ auto r = cell_cache.insert(derived_type);
auto &holes_cell = r.first->second;
if (r.second) {
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc");
if (box_module->get_bool_attribute("\\whitebox")) {
- holes_cell = holes_module->addCell(cell->name, derived_name);
+ holes_cell = holes_module->addCell(cell->name, derived_type);
+
+ if (box_module->has_processes())
+ Pass::call_on_module(design, box_module, "proc");
int box_inputs = 0;
for (auto port_name : box_ports.at(cell->type)) {
@@ -303,7 +341,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
}
}
else if (w->port_output)
- conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
+ conn = holes_module->addWire(stringf("%s.%s", derived_type.c_str(), log_id(port_name)), GetSize(w));
}
// For flops only, create an extra 1-bit input that drives a new wire
@@ -342,59 +380,382 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
}
}
-void reintegrate(RTLIL::Module *module)
+void prep_delays(RTLIL::Design *design, bool dff_mode)
{
- auto design = module->design;
- log_assert(design);
+ TimingInfo timing;
+
+ // Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
+ // (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
+ pool<Module*> flops;
+ std::vector<Cell*> cells;
+ for (auto module : design->selected_modules()) {
+ if (module->processes.size() > 0) {
+ log("Skipping module %s as it contains processes.\n", log_id(module));
+ continue;
+ }
- map_autoidx = autoidx++;
+ for (auto cell : module->cells()) {
+ if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
+ continue;
- RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
- if (mapped_mod == NULL)
- log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
+ RTLIL::Module* inst_module = module->design->module(cell->type);
+ if (!inst_module)
+ continue;
+ if (!inst_module->get_blackbox_attribute())
+ continue;
+ if (inst_module->attributes.count(ID(abc9_box)))
+ continue;
+ IdString derived_type = inst_module->derive(design, cell->parameters);
+ inst_module = design->module(derived_type);
+ log_assert(inst_module);
+
+ if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
+ flops.insert(inst_module);
+ continue; // do not add $__ABC9_DELAY boxes to flops
+ // as delays will be captured in the flop box
+ }
- for (auto w : mapped_mod->wires())
- module->addWire(remap_name(w->name), GetSize(w));
+ if (!timing.count(derived_type))
+ timing.setup_module(inst_module);
- dict<IdString,std::vector<IdString>> box_ports;
+ cells.emplace_back(cell);
+ }
+ }
- for (auto m : design->modules()) {
- if (!m->attributes.count(ID(abc9_box_id)))
+ // Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
+ // with required times
+ for (auto cell : cells) {
+ auto module = cell->module;
+ RTLIL::Module* inst_module = module->design->module(cell->type);
+ log_assert(inst_module);
+ IdString derived_type = inst_module->derive(design, cell->parameters);
+ inst_module = design->module(derived_type);
+ log_assert(inst_module);
+
+ auto &t = timing.at(derived_type).required;
+ for (auto &conn : cell->connections_) {
+ auto port_wire = inst_module->wire(conn.first);
+ if (!port_wire->port_input)
+ continue;
+
+ SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
+ for (int i = 0; i < GetSize(conn.second); i++) {
+ auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
+ if (d == 0)
+ continue;
+
+#ifndef NDEBUG
+ if (ys_debug(1)) {
+ static std::set<std::tuple<IdString,IdString,int>> seen;
+ if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_required = %d\n",
+ log_id(cell->type), log_id(conn.first), i, d);
+ }
+#endif
+ auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
+ box->setPort(ID(I), conn.second[i]);
+ box->setPort(ID(O), O[i]);
+ box->setParam(ID(DELAY), d);
+ conn.second[i] = O[i];
+ }
+ }
+ }
+}
+
+void prep_lut(RTLIL::Design *design, int maxlut)
+{
+ TimingInfo timing;
+
+ std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
+ for (auto module : design->modules()) {
+ auto it = module->attributes.find(ID(abc9_lut));
+ if (it == module->attributes.end())
continue;
- auto r = box_ports.insert(m->name);
+ auto &t = timing.setup_module(module);
+
+ TimingInfo::NameBit o;
+ std::vector<int> specify;
+ for (const auto &i : t.comb) {
+ auto &d = i.first.second;
+ if (o == TimingInfo::NameBit())
+ o = d;
+ else if (o != d)
+ log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
+ specify.push_back(i.second);
+ }
+
+ if (maxlut && GetSize(specify) > maxlut)
+ continue;
+ // ABC requires non-decreasing LUT input delays
+ std::sort(specify.begin(), specify.end());
+ table.emplace_back(GetSize(specify), module->name, it->second.as_int(), std::move(specify));
+ }
+ // ABC requires ascending size
+ std::sort(table.begin(), table.end());
+
+ std::stringstream ss;
+ const auto &first = table.front();
+ // If the first entry does not start from a 1-input LUT,
+ // (as ABC requires) crop the first entry to do so
+ for (int i = 1; i < std::get<0>(first); i++) {
+ ss << "# $__ABC9_LUT" << i << std::endl;
+ ss << i << " " << std::get<2>(first);
+ for (int j = 0; j < i; j++)
+ ss << " " << std::get<3>(first)[j];
+ ss << std::endl;
+ }
+ for (const auto &i : table) {
+ ss << "# " << log_id(std::get<1>(i)) << std::endl;
+ ss << std::get<0>(i) << " " << std::get<2>(i);
+ for (const auto &j : std::get<3>(i))
+ ss << " " << j;
+ ss << std::endl;
+ }
+ design->scratchpad_set_string("abc9_ops.lut_library", ss.str());
+}
+
+void write_lut(RTLIL::Module *module, const std::string &dst) {
+ std::ofstream ofs(dst);
+ log_assert(ofs.is_open());
+ ofs << module->design->scratchpad_get_string("abc9_ops.lut_library");
+ ofs.close();
+}
+
+void prep_box(RTLIL::Design *design, bool dff_mode)
+{
+ TimingInfo timing;
+
+ std::stringstream ss;
+ int abc9_box_id = 1;
+ for (auto module : design->modules()) {
+ auto it = module->attributes.find(ID(abc9_box_id));
+ if (it == module->attributes.end())
+ continue;
+ abc9_box_id = std::max(abc9_box_id, it->second.as_int());
+ }
+
+ dict<IdString,std::vector<IdString>> box_ports;
+ for (auto module : design->modules()) {
+ auto abc9_flop = module->get_bool_attribute(ID(abc9_flop));
+ if (abc9_flop) {
+ auto r = module->attributes.insert(ID(abc9_box_id));
+ if (!r.second)
+ continue;
+ r.first->second = abc9_box_id++;
+
+ if (dff_mode) {
+ int num_inputs = 0, num_outputs = 0;
+ for (auto port_name : module->ports) {
+ auto wire = module->wire(port_name);
+ log_assert(GetSize(wire) == 1);
+ if (wire->port_input) num_inputs++;
+ if (wire->port_output) num_outputs++;
+ }
+ log_assert(num_outputs == 1);
+
+ ss << log_id(module) << " " << r.first->second.as_int();
+ ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+ ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
+
+ ss << "#";
+ bool first = true;
+ for (auto port_name : module->ports) {
+ auto wire = module->wire(port_name);
+ if (!wire->port_input)
+ continue;
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ ss << log_id(wire);
+ }
+ ss << " abc9_ff.Q" << std::endl;
+
+ auto &t = timing.setup_module(module).required;
+ first = true;
+ for (auto port_name : module->ports) {
+ auto wire = module->wire(port_name);
+ if (!wire->port_input)
+ continue;
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ log_assert(GetSize(wire) == 1);
+ auto it = t.find(TimingInfo::NameBit(port_name,0));
+ if (it == t.end())
+ // Assume that no setup time means zero
+ ss << 0;
+ else {
+ ss << it->second;
+
+#ifndef NDEBUG
+ if (ys_debug(1)) {
+ static std::set<std::pair<IdString,IdString>> seen;
+ if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
+ log_id(port_name), it->second);
+ }
+#endif
+ }
+
+ }
+ // Last input is 'abc9_ff.Q'
+ ss << " 0" << std::endl << std::endl;
+ continue;
+ }
+ }
+ else {
+ if (!module->attributes.erase(ID(abc9_box)))
+ continue;
+
+ auto r = module->attributes.insert(ID(abc9_box_id));
+ if (!r.second)
+ continue;
+ r.first->second = abc9_box_id++;
+ }
+
+ auto r = box_ports.insert(module->name);
if (r.second) {
// Make carry in the last PI, and carry out the last PO
// since ABC requires it this way
IdString carry_in, carry_out;
- for (const auto &port_name : m->ports) {
- auto w = m->wire(port_name);
+ for (const auto &port_name : module->ports) {
+ auto w = module->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
- if (w->port_input) {
- if (carry_in != IdString())
- log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
+ log_assert(w->port_input != w->port_output);
+ if (w->port_input)
carry_in = port_name;
- }
- if (w->port_output) {
- if (carry_out != IdString())
- log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
+ else if (w->port_output)
carry_out = port_name;
- }
}
else
r.first->second.push_back(port_name);
}
- if (carry_in != IdString() && carry_out == IdString())
- log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
- if (carry_in == IdString() && carry_out != IdString())
- log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
if (carry_in != IdString()) {
r.first->second.push_back(carry_in);
r.first->second.push_back(carry_out);
}
}
+
+ std::vector<SigBit> inputs;
+ std::vector<SigBit> outputs;
+ for (auto port_name : r.first->second) {
+ auto wire = module->wire(port_name);
+ if (wire->port_input)
+ for (int i = 0; i < GetSize(wire); i++)
+ inputs.emplace_back(wire, i);
+ if (wire->port_output)
+ for (int i = 0; i < GetSize(wire); i++)
+ outputs.emplace_back(wire, i);
+ }
+
+ ss << log_id(module) << " " << module->attributes.at(ID(abc9_box_id)).as_int();
+ ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+ ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
+
+ bool first = true;
+ ss << "#";
+ for (const auto &i : inputs) {
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ if (GetSize(i.wire) == 1)
+ ss << log_id(i.wire);
+ else
+ ss << log_id(i.wire) << "[" << i.offset << "]";
+ }
+ ss << std::endl;
+
+ auto &t = timing.setup_module(module).comb;
+ if (!abc9_flop && t.empty())
+ log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module));
+
+ for (const auto &o : outputs) {
+ first = true;
+ for (const auto &i : inputs) {
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ auto jt = t.find(TimingInfo::BitBit(i,o));
+ if (jt == t.end())
+ ss << "-";
+ else
+ ss << jt->second;
+ }
+ ss << " # ";
+ if (GetSize(o.wire) == 1)
+ ss << log_id(o.wire);
+ else
+ ss << log_id(o.wire) << "[" << o.offset << "]";
+ ss << std::endl;
+
+ }
+ ss << std::endl;
+ }
+
+ // ABC expects at least one box
+ if (ss.tellp() == 0)
+ ss << "(dummy) 1 0 0 0";
+
+ design->scratchpad_set_string("abc9_ops.box_library", ss.str());
+}
+
+void write_box(RTLIL::Module *module, const std::string &dst) {
+ std::ofstream ofs(dst);
+ log_assert(ofs.is_open());
+ ofs << module->design->scratchpad_get_string("abc9_ops.box_library");
+ ofs.close();
+}
+
+void reintegrate(RTLIL::Module *module)
+{
+ auto design = module->design;
+ log_assert(design);
+
+ map_autoidx = autoidx++;
+
+ RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
+ if (mapped_mod == NULL)
+ log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
+
+ for (auto w : mapped_mod->wires())
+ module->addWire(remap_name(w->name), GetSize(w));
+
+ dict<IdString,std::vector<IdString>> box_ports;
+
+ for (auto m : design->modules()) {
+ if (!m->attributes.count(ID(abc9_box_id)))
+ continue;
+
+ auto r = box_ports.insert(m->name);
+ if (!r.second)
+ continue;
+
+ // Make carry in the last PI, and carry out the last PO
+ // since ABC requires it this way
+ IdString carry_in, carry_out;
+ for (const auto &port_name : m->ports) {
+ auto w = m->wire(port_name);
+ log_assert(w);
+ if (w->get_bool_attribute("\\abc9_carry")) {
+ log_assert(w->port_input != w->port_output);
+ if (w->port_input)
+ carry_in = port_name;
+ else if (w->port_output)
+ carry_out = port_name;
+ }
+ else
+ r.first->second.push_back(port_name);
+ }
+
+ if (carry_in != IdString()) {
+ r.first->second.push_back(carry_in);
+ r.first->second.push_back(carry_out);
+ }
}
std::vector<Cell*> boxes;
@@ -465,16 +826,6 @@ void reintegrate(RTLIL::Module *module)
}
if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
- // Convert buffer into direct connection
- if (mapped_cell->type == ID($lut) &&
- GetSize(mapped_cell->getPort(ID::A)) == 1 &&
- mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
- SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
- SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
- module->connect(my_y, my_a);
- log_abort();
- continue;
- }
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
cell->parameters = mapped_cell->parameters;
cell->attributes = mapped_cell->attributes;
@@ -506,12 +857,25 @@ void reintegrate(RTLIL::Module *module)
}
else {
RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
- log_assert(existing_cell);
+ if (!existing_cell)
+ log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
+
+ if (existing_cell->type == ID($__ABC9_DELAY)) {
+ SigBit I = mapped_cell->getPort(ID(i));
+ SigBit O = mapped_cell->getPort(ID(o));
+ if (I.wire)
+ I.wire = module->wires_.at(remap_name(I.wire->name));
+ log_assert(O.wire);
+ O.wire = module->wires_.at(remap_name(O.wire->name));
+ module->connect(O, I);
+ continue;
+ }
RTLIL::Module* box_module = design->module(existing_cell->type);
- auto it = box_module->attributes.find(ID(abc9_box_id));
- log_assert(it != box_module->attributes.end());
- log_assert(mapped_cell->type == stringf("$__boxid%d", it->second.as_int()));
+ IdString derived_type = box_module->derive(design, existing_cell->parameters);
+ RTLIL::Module* derived_module = design->module(derived_type);
+ log_assert(derived_module);
+ log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
mapped_cell->type = existing_cell->type;
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
@@ -539,7 +903,7 @@ void reintegrate(RTLIL::Module *module)
}
int input_count = 0, output_count = 0;
- for (const auto &port_name : box_ports.at(cell->type)) {
+ for (const auto &port_name : box_ports.at(derived_type)) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
@@ -729,6 +1093,14 @@ struct Abc9OpsPass : public Pass {
log("mapping, and is expected to be called in conjunction with other operations from\n");
log("the `abc9' script pass. Only fully-selected modules are supported.\n");
log("\n");
+ log(" -check\n");
+ log(" check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
+ log(" (* abc9_carry *) is only given for one input/output port, etc.\n");
+ log("\n");
+ log(" -prep_delays\n");
+ log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
+ log(" certain required times.\n");
+ log("\n");
log(" -mark_scc\n");
log(" for an arbitrarily chosen cell in each unique SCC of each selected module\n");
log(" (tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all\n");
@@ -742,13 +1114,27 @@ struct Abc9OpsPass : public Pass {
log(" whiteboxes.\n");
log("\n");
log(" -dff\n");
- log(" consider flop cells (those instantiating modules marked with (* abc9_flop *)\n");
- log(" during -prep_xaiger.\n");
+ log(" consider flop cells (those instantiating modules marked with (* abc9_flop *))\n");
+ log(" during -prep_{delays,xaiger,box}.\n");
log("\n");
log(" -prep_dff\n");
log(" compute the clock domain and initial value of each flop in the design.\n");
log(" process the '$holes' module to support clock-enable functionality.\n");
log("\n");
+ log(" -prep_lut <maxlut>\n");
+ log(" pre-compute the lut library by analysing all modules marked with\n");
+ log(" (* abc9_lut=<area> *).\n");
+ log("\n");
+ log(" -write_lut <dst>\n");
+ log(" write the pre-computed lut library to <dst>.\n");
+ log("\n");
+ log(" -prep_box\n");
+ log(" pre-compute the box library by analysing all modules marked with\n");
+ log(" (* abc9_box *).\n");
+ log("\n");
+ log(" -write_box <dst>\n");
+ log(" write the pre-computed box library to <dst>.\n");
+ log("\n");
log(" -reintegrate\n");
log(" for each selected module, re-intergrate the module '<module-name>$abc9'\n");
log(" by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
@@ -759,15 +1145,26 @@ struct Abc9OpsPass : public Pass {
{
log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
+ bool check_mode = false;
+ bool prep_delays_mode = false;
bool mark_scc_mode = false;
bool prep_dff_mode = false;
bool prep_xaiger_mode = false;
+ bool prep_lut_mode = false;
+ bool prep_box_mode = false;
bool reintegrate_mode = false;
bool dff_mode = false;
+ std::string write_lut_dst;
+ int maxlut = 0;
+ std::string write_box_dst;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
+ if (arg == "-check") {
+ check_mode = true;
+ continue;
+ }
if (arg == "-mark_scc") {
mark_scc_mode = true;
continue;
@@ -780,6 +1177,32 @@ struct Abc9OpsPass : public Pass {
prep_xaiger_mode = true;
continue;
}
+ if (arg == "-prep_delays") {
+ prep_delays_mode = true;
+ continue;
+ }
+ if (arg == "-prep_lut" && argidx+1 < args.size()) {
+ prep_lut_mode = true;
+ maxlut = atoi(args[++argidx].c_str());
+ continue;
+ }
+ if (arg == "-maxlut" && argidx+1 < args.size()) {
+ continue;
+ }
+ if (arg == "-write_lut" && argidx+1 < args.size()) {
+ write_lut_dst = args[++argidx];
+ rewrite_filename(write_lut_dst);
+ continue;
+ }
+ if (arg == "-prep_box") {
+ prep_box_mode = true;
+ continue;
+ }
+ if (arg == "-write_box" && argidx+1 < args.size()) {
+ write_box_dst = args[++argidx];
+ rewrite_filename(write_box_dst);
+ continue;
+ }
if (arg == "-reintegrate") {
reintegrate_mode = true;
continue;
@@ -792,11 +1215,20 @@ struct Abc9OpsPass : public Pass {
}
extra_args(args, argidx, design);
- if (!(mark_scc_mode || prep_dff_mode || reintegrate_mode))
- log_cmd_error("At least one of -mark_scc, -prep_{xaiger,dff}, -reintegrate must be specified.\n");
+ if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
+ log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
+
+ if (dff_mode && !prep_delays_mode && !prep_xaiger_mode && !prep_box_mode)
+ log_cmd_error("'-dff' option is only relevant for -prep_{delay,xaiger,box}.\n");
- if (dff_mode && !prep_xaiger_mode)
- log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
+ if (check_mode)
+ check(design);
+ if (prep_delays_mode)
+ prep_delays(design, dff_mode);
+ if (prep_lut_mode)
+ prep_lut(design, maxlut);
+ if (prep_box_mode)
+ prep_box(design, dff_mode);
for (auto mod : design->selected_modules()) {
if (mod->get_bool_attribute("\\abc9_holes"))
@@ -810,6 +1242,10 @@ struct Abc9OpsPass : public Pass {
if (!design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", log_id(mod));
+ if (!write_lut_dst.empty())
+ write_lut(mod, write_lut_dst);
+ if (!write_box_dst.empty())
+ write_box(mod, write_box_dst);
if (mark_scc_mode)
mark_scc(mod);
if (prep_dff_mode)
diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc
index 17a99493d..639ae145b 100644
--- a/passes/techmap/extract_counter.cc
+++ b/passes/techmap/extract_counter.cc
@@ -90,22 +90,35 @@ bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
struct CounterExtraction
{
int width; //counter width
+ bool count_is_up; //count up (else down)
RTLIL::Wire* rwire; //the register output
bool has_reset; //true if we have a reset
bool has_ce; //true if we have a clock enable
+ bool ce_inverted; //true if clock enable is active low
RTLIL::SigSpec rst; //reset pin
bool rst_inverted; //true if reset is active low
bool rst_to_max; //true if we reset to max instead of 0
int count_value; //value we count from
RTLIL::SigSpec ce; //clock signal
RTLIL::SigSpec clk; //clock enable, if any
- RTLIL::SigSpec outsig; //counter output signal
+ RTLIL::SigSpec outsig; //counter overflow output signal
+ RTLIL::SigSpec poutsig; //counter parallel output signal
+ bool has_pout; //whether parallel output is used
RTLIL::Cell* count_mux; //counter mux
RTLIL::Cell* count_reg; //counter register
- RTLIL::Cell* underflow_inv; //inverter reduction for output-underflow detect
+ RTLIL::Cell* overflow_cell; //cell for counter overflow (either inverter reduction or $eq)
pool<ModIndex::PortInfo> pouts; //Ports that take a parallel output from us
};
+struct CounterExtractionSettings
+{
+ pool<RTLIL::IdString>& parallel_cells;
+ int maxwidth;
+ int minwidth;
+ bool allow_arst;
+ int allowed_dirs; //0 = down, 1 = up, 2 = both
+};
+
//attempt to extract a counter centered on the given adder cell
//For now we only support DOWN counters.
//TODO: up/down support
@@ -113,49 +126,132 @@ int counter_tryextract(
ModIndex& index,
Cell *cell,
CounterExtraction& extract,
- pool<RTLIL::IdString>& parallel_cells,
- int maxwidth)
+ CounterExtractionSettings settings)
{
SigMap& sigmap = index.sigmap;
- //A counter with less than 2 bits makes no sense
- //TODO: configurable min threshold
- int a_width = cell->getParam(ID(A_WIDTH)).as_int();
- extract.width = a_width;
- if( (a_width < 2) || (a_width > maxwidth) )
- return 1;
-
- //Second input must be a single bit
- int b_width = cell->getParam(ID(B_WIDTH)).as_int();
- if(b_width != 1)
- return 2;
-
//Both inputs must be unsigned, so don't extract anything with a signed input
bool a_sign = cell->getParam(ID(A_SIGNED)).as_bool();
bool b_sign = cell->getParam(ID(B_SIGNED)).as_bool();
if(a_sign || b_sign)
return 3;
- //To be a counter, one input of the ALU must be a constant 1
- //TODO: can A or B be swapped in synthesized RTL or is B always the 1?
- const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
- if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
- return 4;
-
- //BI and CI must be constant 1 as well
- const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID(BI)));
- if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
- return 5;
- const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID(CI)));
- if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
- return 6;
-
//CO and X must be unconnected (exactly one connection to each port)
if(!is_unconnected(sigmap(cell->getPort(ID(CO))), index))
return 7;
if(!is_unconnected(sigmap(cell->getPort(ID(X))), index))
return 8;
+ //true if $alu is performing A - B, else A + B
+ bool alu_is_subtract;
+
+ //BI and CI must be both constant 0 or both constant 1 as well
+ const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID(BI)));
+ const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID(CI)));
+ if(bi_port.is_fully_const() && bi_port.as_int() == 1 &&
+ ci_port.is_fully_const() && ci_port.as_int() == 1)
+ {
+ alu_is_subtract = true;
+ }
+ else if(bi_port.is_fully_const() && bi_port.as_int() == 0 &&
+ ci_port.is_fully_const() && ci_port.as_int() == 0)
+ {
+ alu_is_subtract = false;
+ }
+ else
+ {
+ return 5;
+ }
+
+ //false -> port B connects to value
+ //true -> port A connects to value
+ bool alu_port_use_a = false;
+
+ if(alu_is_subtract)
+ {
+ const int a_width = cell->getParam(ID(A_WIDTH)).as_int();
+ const int b_width = cell->getParam(ID(B_WIDTH)).as_int();
+ const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
+
+ // down, cnt <= cnt - 1
+ if (b_width == 1 && b_port.is_fully_const() && b_port.as_int() == 1)
+ {
+ // OK
+ alu_port_use_a = true;
+ extract.count_is_up = false;
+ }
+
+ // up, cnt <= cnt - -1
+ else if (b_width == a_width && b_port.is_fully_const() && b_port.is_fully_ones())
+ {
+ // OK
+ alu_port_use_a = true;
+ extract.count_is_up = true;
+ }
+
+ // ???
+ else
+ {
+ return 2;
+ }
+ }
+ else
+ {
+ const int a_width = cell->getParam(ID(A_WIDTH)).as_int();
+ const int b_width = cell->getParam(ID(B_WIDTH)).as_int();
+ const RTLIL::SigSpec a_port = sigmap(cell->getPort(ID::A));
+ const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
+
+ // down, cnt <= cnt + -1
+ if (b_width == a_width && b_port.is_fully_const() && b_port.is_fully_ones())
+ {
+ // OK
+ alu_port_use_a = true;
+ extract.count_is_up = false;
+ }
+ else if (a_width == b_width && a_port.is_fully_const() && a_port.is_fully_ones())
+ {
+ // OK
+ alu_port_use_a = false;
+ extract.count_is_up = false;
+ }
+
+ // up, cnt <= cnt + 1
+ else if (b_width == 1 && b_port.is_fully_const() && b_port.as_int() == 1)
+ {
+ // OK
+ alu_port_use_a = true;
+ extract.count_is_up = true;
+ }
+ else if (a_width == 1 && a_port.is_fully_const() && a_port.as_int() == 1)
+ {
+ // OK
+ alu_port_use_a = false;
+ extract.count_is_up = true;
+ }
+
+ // ???
+ else
+ {
+ return 2;
+ }
+ }
+
+ if (extract.count_is_up && settings.allowed_dirs == 0)
+ return 26;
+ if (!extract.count_is_up && settings.allowed_dirs == 1)
+ return 26;
+
+ //Check if counter is an appropriate size
+ int count_width;
+ if (alu_port_use_a)
+ count_width = cell->getParam(ID(A_WIDTH)).as_int();
+ else
+ count_width = cell->getParam(ID(B_WIDTH)).as_int();
+ extract.width = count_width;
+ if( (count_width < settings.minwidth) || (count_width > settings.maxwidth) )
+ return 1;
+
//Y must have exactly one connection, and it has to be a $mux cell.
//We must have a direct bus connection from our Y to their A.
const RTLIL::SigSpec aluy = sigmap(cell->getPort(ID::Y));
@@ -169,30 +265,43 @@ int counter_tryextract(
if(!is_full_bus(aluy, index, cell, ID::Y, count_mux, ID::A))
return 11;
- //B connection of the mux is our underflow value
- const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B));
- if(!underflow.is_fully_const())
- return 12;
- extract.count_value = underflow.as_int();
+ if (extract.count_is_up)
+ {
+ //B connection of the mux must be 0
+ const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B));
+ if(!(underflow.is_fully_const() && underflow.is_fully_zero()))
+ return 12;
+ }
+ else
+ {
+ //B connection of the mux is our underflow value
+ const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B));
+ if(!underflow.is_fully_const())
+ return 12;
+ extract.count_value = underflow.as_int();
+ }
- //S connection of the mux must come from an inverter (need not be the only load)
+ //S connection of the mux must come from an inverter if down, eq if up
+ //(need not be the only load)
const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID(S)));
extract.outsig = muxsel;
pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
- Cell* underflow_inv = NULL;
+ Cell* overflow_cell = NULL;
for(auto c : muxsel_conns)
{
- if(c->type != ID($logic_not))
+ if(extract.count_is_up && c->type != ID($eq))
+ continue;
+ if(!extract.count_is_up && c->type != ID($logic_not))
continue;
if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID(S), true))
continue;
- underflow_inv = c;
+ overflow_cell = c;
break;
}
- if(underflow_inv == NULL)
+ if(overflow_cell == NULL)
return 13;
- extract.underflow_inv = underflow_inv;
+ extract.overflow_cell = overflow_cell;
//Y connection of the mux must have exactly one load, the counter's internal register, if there's no clock enable
//If we have a clock enable, Y drives the B input of a mux. A of that mux must come from our register
@@ -215,14 +324,24 @@ int counter_tryextract(
return 24;
count_reg = *cey_loads.begin();
- //Mux should have A driven by count Q, and B by muxy
- //TODO: if A and B are swapped, CE polarity is inverted
- if(sigmap(cemux->getPort(ID::B)) != muxy)
- return 24;
- if(sigmap(cemux->getPort(ID::A)) != sigmap(count_reg->getPort(ID(Q))))
- return 24;
if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID(D))))
return 24;
+ //Mux should have A driven by count Q, and B by muxy
+ //if A and B are swapped, CE polarity is inverted
+ if(sigmap(cemux->getPort(ID::B)) == muxy &&
+ sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID(Q))))
+ {
+ extract.ce_inverted = false;
+ }
+ else if(sigmap(cemux->getPort(ID::A)) == muxy &&
+ sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID(Q))))
+ {
+ extract.ce_inverted = true;
+ }
+ else
+ {
+ return 24;
+ }
//Select of the mux is our clock enable
extract.has_ce = true;
@@ -236,6 +355,9 @@ int counter_tryextract(
extract.has_reset = false;
else if(count_reg->type == ID($adff))
{
+ if (!settings.allow_arst)
+ return 25;
+
extract.has_reset = true;
//Check polarity of reset - we may have to add an inverter later on!
@@ -260,7 +382,9 @@ int counter_tryextract(
//Sanity check that we use the ALU output properly
if(extract.has_ce)
{
- if(!is_full_bus(muxy, index, count_mux, ID::Y, cemux, ID::B))
+ if(!extract.ce_inverted && !is_full_bus(muxy, index, count_mux, ID::Y, cemux, ID::B))
+ return 16;
+ if(extract.ce_inverted && !is_full_bus(muxy, index, count_mux, ID::Y, cemux, ID::A))
return 16;
if(!is_full_bus(cey, index, cemux, ID::Y, count_reg, ID(D)))
return 16;
@@ -274,6 +398,8 @@ int counter_tryextract(
//(unless we have a parallel output!)
//If we have a clock enable, 3 is OK
const RTLIL::SigSpec qport = count_reg->getPort(ID(Q));
+ extract.poutsig = qport;
+ extract.has_pout = false;
const RTLIL::SigSpec cnout = sigmap(qport);
pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
unsigned int max_loads = 2;
@@ -283,7 +409,7 @@ int counter_tryextract(
{
for(auto c : cnout_loads)
{
- if(c == underflow_inv)
+ if(c == overflow_cell)
continue;
if(c == cell)
continue;
@@ -291,15 +417,16 @@ int counter_tryextract(
continue;
//If we specified a limited set of cells for parallel output, check that we only drive them
- if(!parallel_cells.empty())
+ if(!settings.parallel_cells.empty())
{
//Make sure we're in the whitelist
- if( parallel_cells.find(c->type) == parallel_cells.end())
+ if( settings.parallel_cells.find(c->type) == settings.parallel_cells.end())
return 17;
}
//Figure out what port(s) are driven by it
//TODO: this can probably be done more efficiently w/o multiple iterations over our whole net?
+ //TODO: For what purpose do we actually need extract.pouts?
for(auto b : qport)
{
pool<ModIndex::PortInfo> ports = index.query_ports(b);
@@ -308,25 +435,75 @@ int counter_tryextract(
if(x.cell != c)
continue;
extract.pouts.insert(ModIndex::PortInfo(c, x.port, 0));
+ extract.has_pout = true;
}
}
}
}
- if(!is_full_bus(cnout, index, count_reg, ID(Q), underflow_inv, ID::A, true))
- return 18;
- if(!is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true))
+ for (auto b : qport)
+ {
+ if(index.query_is_output(b))
+ {
+ // Parallel out goes out of module
+ extract.has_pout = true;
+ }
+ }
+ if(!extract.count_is_up)
+ {
+ if(!is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true))
+ return 18;
+ }
+ else
+ {
+ if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true))
+ {
+ // B must be the overflow value
+ const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::B));
+ if(!overflow.is_fully_const())
+ return 12;
+ extract.count_value = overflow.as_int();
+ }
+ else if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::B, true))
+ {
+ // A must be the overflow value
+ const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::A));
+ if(!overflow.is_fully_const())
+ return 12;
+ extract.count_value = overflow.as_int();
+ }
+ else
+ {
+ return 18;
+ }
+ }
+ if(alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true))
+ return 19;
+ if(!alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::B, true))
return 19;
//Look up the clock from the register
extract.clk = sigmap(count_reg->getPort(ID(CLK)));
- //Register output net must have an INIT attribute equal to the count value
- extract.rwire = cnout.as_wire();
- if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
- return 20;
- int rinit = extract.rwire->attributes[ID(init)].as_int();
- if(rinit != extract.count_value)
- return 21;
+ if(!extract.count_is_up)
+ {
+ //Register output net must have an INIT attribute equal to the count value
+ extract.rwire = cnout.as_wire();
+ if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
+ return 20;
+ int rinit = extract.rwire->attributes[ID(init)].as_int();
+ if(rinit != extract.count_value)
+ return 21;
+ }
+ else
+ {
+ //Register output net must not have an INIT attribute or it must be zero
+ extract.rwire = cnout.as_wire();
+ if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
+ return 0;
+ int rinit = extract.rwire->attributes[ID(init)].as_int();
+ if(rinit != 0)
+ return 21;
+ }
return 0;
}
@@ -337,8 +514,7 @@ void counter_worker(
unsigned int& total_counters,
pool<Cell*>& cells_to_remove,
pool<pair<Cell*, string>>& cells_to_rename,
- pool<RTLIL::IdString>& parallel_cells,
- int maxwidth)
+ CounterExtractionSettings settings)
{
SigMap& sigmap = index.sigmap;
@@ -350,20 +526,24 @@ void counter_worker(
//If it's not a wire, don't even try
auto port = sigmap(cell->getPort(ID::A));
if(!port.is_wire())
- return;
- RTLIL::Wire* a_wire = port.as_wire();
+ {
+ port = sigmap(cell->getPort(ID::B));
+ if(!port.is_wire())
+ return;
+ }
+ RTLIL::Wire* port_wire = port.as_wire();
bool force_extract = false;
bool never_extract = false;
- string count_reg_src = a_wire->attributes[ID(src)].decode_string().c_str();
- if(a_wire->attributes.find(ID(COUNT_EXTRACT)) != a_wire->attributes.end())
+ string count_reg_src = port_wire->attributes[ID(src)].decode_string().c_str();
+ if(port_wire->attributes.find(ID(COUNT_EXTRACT)) != port_wire->attributes.end())
{
- pool<string> sa = a_wire->get_strpool_attribute(ID(COUNT_EXTRACT));
+ pool<string> sa = port_wire->get_strpool_attribute(ID(COUNT_EXTRACT));
string extract_value;
if(sa.size() >= 1)
{
extract_value = *sa.begin();
log(" Signal %s declared at %s has COUNT_EXTRACT = %s\n",
- log_id(a_wire),
+ log_id(port_wire),
count_reg_src.c_str(),
extract_value.c_str());
@@ -385,21 +565,21 @@ void counter_worker(
//Attempt to extract a counter
CounterExtraction extract;
- int reason = counter_tryextract(index, cell, extract, parallel_cells, maxwidth);
+ int reason = counter_tryextract(index, cell, extract, settings);
//Nonzero code - we could not find a matchable counter.
//Do nothing, unless extraction was forced in which case give an error
if(reason != 0)
{
- static const char* reasons[25]=
+ static const char* reasons[]=
{
"no problem", //0
"counter is too large/small", //1
"counter does not count by one", //2
"counter uses signed math", //3
- "counter does not count by one", //4
- "ALU is not a subtractor", //5
- "ALU is not a subtractor", //6
+ "RESERVED, not implemented", //4
+ "ALU is not an adder/subtractor", //5
+ "RESERVED, not implemented", //6
"ALU ports used outside counter", //7
"ALU ports used outside counter", //8
"ALU output used outside counter", //9
@@ -417,14 +597,16 @@ void counter_worker(
"Underflow value is not equal to init value", //21
"RESERVED, not implemented", //22, kept for compatibility but not used anymore
"Reset is not to zero or COUNT_TO", //23
- "Clock enable configuration is unsupported" //24
+ "Clock enable configuration is unsupported", //24
+ "Async reset used but not permitted", //25
+ "Count direction is not allowed" //26
};
if(force_extract)
{
log_error(
"Counter extraction is set to FORCE on register %s, but a counter could not be inferred (%s)\n",
- log_id(a_wire),
+ log_id(port_wire),
reasons[reason]);
}
return;
@@ -483,36 +665,53 @@ void counter_worker(
if(extract.has_ce)
{
cell->setParam(ID(HAS_CE), RTLIL::Const(1));
- cell->setPort(ID(CE), extract.ce);
+ if(extract.ce_inverted)
+ {
+ auto realce = cell->module->addWire(NEW_ID);
+ cell->module->addNot(NEW_ID, extract.ce, RTLIL::SigSpec(realce));
+ cell->setPort(ID(CE), realce);
+ }
+ else
+ cell->setPort(ID(CE), extract.ce);
}
else
+ {
cell->setParam(ID(HAS_CE), RTLIL::Const(0));
+ cell->setPort(ID(CE), RTLIL::Const(1));
+ }
+
+ if(extract.count_is_up)
+ {
+ cell->setParam(ID(DIRECTION), RTLIL::Const("UP"));
+ //XXX: What is this supposed to do?
+ cell->setPort(ID(UP), RTLIL::Const(1));
+ }
+ else
+ {
+ cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN"));
+ cell->setPort(ID(UP), RTLIL::Const(0));
+ }
- //Hook up hard-wired ports (for now up/down are not supported), default to no parallel output
+ //Hook up hard-wired ports, default to no parallel output
cell->setParam(ID(HAS_POUT), RTLIL::Const(0));
cell->setParam(ID(RESET_TO_MAX), RTLIL::Const(0));
- cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN"));
- cell->setPort(ID(CE), RTLIL::Const(1));
- cell->setPort(ID(UP), RTLIL::Const(0));
//Hook up any parallel outputs
for(auto load : extract.pouts)
{
log(" Counter has parallel output to cell %s port %s\n", log_id(load.cell->name), log_id(load.port));
-
- //Find the wire hooked to the old port
- auto sig = load.cell->getPort(load.port);
-
+ }
+ if(extract.has_pout)
+ {
//Connect it to our parallel output
- //(this is OK to do more than once b/c they all go to the same place)
- cell->setPort(ID(POUT), sig);
+ cell->setPort(ID(POUT), extract.poutsig);
cell->setParam(ID(HAS_POUT), RTLIL::Const(1));
}
//Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires)
cells_to_remove.insert(extract.count_mux);
cells_to_remove.insert(extract.count_reg);
- cells_to_remove.insert(extract.underflow_inv);
+ cells_to_remove.insert(extract.overflow_cell);
//Log it
total_counters ++;
@@ -527,17 +726,19 @@ void counter_worker(
//TODO: support other kind of reset
reset_type += " async resettable";
}
- log(" Found %d-bit (%s) down counter %s (counting from %d) for register %s, declared at %s\n",
+ log(" Found %d-bit (%s) %s counter %s (counting %s %d) for register %s, declared at %s\n",
extract.width,
reset_type.c_str(),
+ extract.count_is_up ? "up" : "down",
countname.c_str(),
+ extract.count_is_up ? "to" : "from",
extract.count_value,
log_id(extract.rwire->name),
count_reg_src.c_str());
//Optimize the counter
//If we have no parallel output, and we have redundant bits, shrink us
- if(extract.pouts.empty())
+ if(!extract.has_pout)
{
//TODO: Need to update this when we add support for counters with nonzero reset values
//to make sure the reset value fits in our bit space too
@@ -570,7 +771,16 @@ struct ExtractCounterPass : public Pass {
log("to the actual target cells.\n");
log("\n");
log(" -maxwidth N\n");
- log(" Only extract counters up to N bits wide\n");
+ log(" Only extract counters up to N bits wide (default 64)\n");
+ log("\n");
+ log(" -minwidth N\n");
+ log(" Only extract counters at least N bits wide (default 2)\n");
+ log("\n");
+ log(" -allow_arst yes|no\n");
+ log(" Allow counters to have async reset (default yes)\n");
+ log("\n");
+ log(" -dir up|down|both\n");
+ log(" Look for up-counters, down-counters, or both (default down)\n");
log("\n");
log(" -pout X,Y,...\n");
log(" Only allow parallel output from the counter to the listed cell types\n");
@@ -582,9 +792,17 @@ struct ExtractCounterPass : public Pass {
{
log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n");
- int maxwidth = 64;
+ pool<RTLIL::IdString> _parallel_cells;
+ CounterExtractionSettings settings
+ {
+ .parallel_cells = _parallel_cells,
+ .maxwidth = 64,
+ .minwidth = 2,
+ .allow_arst = true,
+ .allowed_dirs = 0,
+ };
+
size_t argidx;
- pool<RTLIL::IdString> parallel_cells;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-pout")
@@ -601,24 +819,63 @@ struct ExtractCounterPass : public Pass {
{
if(pouts[i] == ',')
{
- parallel_cells.insert(RTLIL::escape_id(tmp));
+ settings.parallel_cells.insert(RTLIL::escape_id(tmp));
tmp = "";
}
else
tmp += pouts[i];
}
- parallel_cells.insert(RTLIL::escape_id(tmp));
+ settings.parallel_cells.insert(RTLIL::escape_id(tmp));
continue;
}
if (args[argidx] == "-maxwidth" && argidx+1 < args.size())
{
- maxwidth = atoi(args[++argidx].c_str());
+ settings.maxwidth = atoi(args[++argidx].c_str());
+ continue;
+ }
+
+ if (args[argidx] == "-minwidth" && argidx+1 < args.size())
+ {
+ settings.minwidth = atoi(args[++argidx].c_str());
+ continue;
+ }
+
+ if (args[argidx] == "-allow_arst" && argidx+1 < args.size())
+ {
+ auto arg = args[++argidx];
+ if (arg == "yes")
+ settings.allow_arst = true;
+ else if (arg == "no")
+ settings.allow_arst = false;
+ else
+ log_error("Invalid -allow_arst value \"%s\"\n", arg.c_str());
+ continue;
+ }
+
+ if (args[argidx] == "-dir" && argidx+1 < args.size())
+ {
+ auto arg = args[++argidx];
+ if (arg == "up")
+ settings.allowed_dirs = 1;
+ else if (arg == "down")
+ settings.allowed_dirs = 0;
+ else if (arg == "both")
+ settings.allowed_dirs = 2;
+ else
+ log_error("Invalid -dir value \"%s\"\n", arg.c_str());
continue;
}
}
extra_args(args, argidx, design);
+ if (settings.minwidth < 2)
+ {
+ //A counter with less than 2 bits makes no sense
+ log_warning("Minimum counter width is 2 bits wide\n");
+ settings.minwidth = 2;
+ }
+
//Extract all of the counters we could find
unsigned int total_counters = 0;
for (auto module : design->selected_modules())
@@ -628,7 +885,7 @@ struct ExtractCounterPass : public Pass {
ModIndex index(module);
for (auto cell : module->selected_cells())
- counter_worker(index, cell, total_counters, cells_to_remove, cells_to_rename, parallel_cells, maxwidth);
+ counter_worker(index, cell, total_counters, cells_to_remove, cells_to_rename, settings);
for(auto cell : cells_to_remove)
{
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 531ac2b99..f63012d1a 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -83,6 +83,20 @@ struct IopadmapPass : public Pass {
log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
log("\n");
}
+
+ void module_queue(Design *design, Module *module, std::vector<Module *> &modules_sorted, pool<Module *> &modules_processed) {
+ if (modules_processed.count(module))
+ return;
+ for (auto cell : module->cells()) {
+ Module *submodule = design->module(cell->type);
+ if (!submodule)
+ continue;
+ module_queue(design, submodule, modules_sorted, modules_processed);
+ }
+ modules_sorted.push_back(module);
+ modules_processed.insert(module);
+ }
+
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
@@ -172,22 +186,49 @@ struct IopadmapPass : public Pass {
if (!tinoutpad_portname_pad.empty())
ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname_pad)));
- for (auto module : design->modules())
- if (module->get_blackbox_attribute())
- for (auto wire : module->wires())
- if (wire->get_bool_attribute("\\iopad_external_pin"))
- ignore.insert(make_pair(module->name, wire->name));
+ // Recursively collect list of (module, port, bit) triples that already have buffers.
+
+ pool<pair<IdString, pair<IdString, int>>> buf_ports;
+ // Process submodules before module using them.
+ std::vector<Module *> modules_sorted;
+ pool<Module *> modules_processed;
for (auto module : design->selected_modules())
+ module_queue(design, module, modules_sorted, modules_processed);
+
+ for (auto module : modules_sorted)
{
- pool<SigBit> skip_wire_bits;
- dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits;
+ pool<SigBit> buf_bits;
+ SigMap sigmap(module);
+ // Collect explicitly-marked already-buffered SigBits.
+ for (auto wire : module->wires())
+ if (wire->get_bool_attribute("\\iopad_external_pin") || ignore.count(make_pair(module->name, wire->name)))
+ for (int i = 0; i < GetSize(wire); i++)
+ buf_bits.insert(sigmap(SigBit(wire, i)));
+
+ // Collect SigBits connected to already-buffered ports.
for (auto cell : module->cells())
for (auto port : cell->connections())
- if (ignore.count(make_pair(cell->type, port.first)))
- for (auto bit : port.second)
- skip_wire_bits.insert(bit);
+ for (int i = 0; i < port.second.size(); i++)
+ if (buf_ports.count(make_pair(cell->type, make_pair(port.first, i))))
+ buf_bits.insert(sigmap(port.second[i]));
+
+ // Now fill buf_ports.
+ for (auto wire : module->wires())
+ if (wire->port_input || wire->port_output)
+ for (int i = 0; i < GetSize(wire); i++)
+ if (buf_bits.count(sigmap(SigBit(wire, i)))) {
+ buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+ log("Marking already mapped port: %s.%s[%d].\n", log_id(module), log_id(wire), i);
+ }
+ }
+
+ // Now do the actual buffer insertion.
+
+ for (auto module : design->selected_modules())
+ {
+ dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits;
if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
{
@@ -234,7 +275,7 @@ struct IopadmapPass : public Pass {
SigBit wire_bit(wire, i);
Cell *tbuf_cell = nullptr;
- if (skip_wire_bits.count(wire_bit))
+ if (buf_ports.count(make_pair(module->name, make_pair(wire->name, i))))
continue;
if (tbuf_bits.count(wire_bit))
@@ -282,7 +323,6 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(tinoutpad_portname_o), wire_bit);
cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), data_sig);
}
- skip_wire_bits.insert(wire_bit);
if (!tinoutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad));
} else {
@@ -298,10 +338,10 @@ struct IopadmapPass : public Pass {
module->remove(tbuf_cell);
module->connect(wire_bit, data_sig);
}
- skip_wire_bits.insert(wire_bit);
if (!toutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(toutpad_portname_pad));
}
+ buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
}
}
}
@@ -315,7 +355,7 @@ struct IopadmapPass : public Pass {
pool<int> skip_bit_indices;
for (int i = 0; i < GetSize(wire); i++)
- if (skip_wire_bits.count(SigBit(wire, i)))
+ if (buf_ports.count(make_pair(module->name, make_pair(wire->name, i))))
skip_bit_indices.insert(i);
if (GetSize(wire) == GetSize(skip_bit_indices))
@@ -423,6 +463,15 @@ struct IopadmapPass : public Pass {
}
}
+ if (wire->port_output) {
+ auto jt = new_wire->attributes.find(ID(init));
+ // For output ports, move \init attributes from old wire to new wire
+ if (jt != new_wire->attributes.end()) {
+ wire->attributes[ID(init)] = std::move(jt->second);
+ new_wire->attributes.erase(jt);
+ }
+ }
+
wire->port_id = 0;
wire->port_input = false;
wire->port_output = false;
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-09 18:30:51 +0000