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-rw-r--r--passes/pmgen/.gitignore2
-rw-r--r--passes/pmgen/Makefile.inc6
-rw-r--r--passes/pmgen/ice40_dsp.cc132
-rw-r--r--passes/pmgen/ice40_dsp.pmg254
-rw-r--r--passes/pmgen/xilinx_dsp.cc243
-rw-r--r--passes/pmgen/xilinx_dsp.pmg273
-rw-r--r--passes/techmap/abc9.cc58
-rw-r--r--passes/techmap/techmap.cc44
-rw-r--r--passes/tests/test_autotb.cc5
9 files changed, 861 insertions, 156 deletions
diff --git a/passes/pmgen/.gitignore b/passes/pmgen/.gitignore
index 6b319b8c3..e52f3282f 100644
--- a/passes/pmgen/.gitignore
+++ b/passes/pmgen/.gitignore
@@ -1 +1 @@
-/*_pm.h \ No newline at end of file
+/*_pm.h
diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 6648e2ec0..fcbaa99ed 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -21,6 +21,12 @@ $(eval $(call add_extra_objs,passes/pmgen/ice40_wrapcarry_pm.h))
# --------------------------------------
+OBJS += passes/pmgen/xilinx_dsp.o
+passes/pmgen/xilinx_dsp.o: passes/pmgen/xilinx_dsp_pm.h
+$(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_pm.h))
+
+# --------------------------------------
+
OBJS += passes/pmgen/peepopt.o
passes/pmgen/peepopt.o: passes/pmgen/peepopt_pm.h
$(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h))
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 16bfe537f..31e11c742 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -29,15 +29,16 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
{
auto &st = pm.st_ice40_dsp;
-#if 0
+#if 1
log("\n");
- log("ffA: %s\n", log_id(st.ffA, "--"));
- log("ffB: %s\n", log_id(st.ffB, "--"));
- log("mul: %s\n", log_id(st.mul, "--"));
- log("ffY: %s\n", log_id(st.ffY, "--"));
- log("addAB: %s\n", log_id(st.addAB, "--"));
- log("muxAB: %s\n", log_id(st.muxAB, "--"));
- log("ffS: %s\n", log_id(st.ffS, "--"));
+ log("ffA: %s\n", log_id(st.ffA, "--"));
+ log("ffB: %s\n", log_id(st.ffB, "--"));
+ log("mul: %s\n", log_id(st.mul, "--"));
+ log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
+ log("addAB: %s\n", log_id(st.addAB, "--"));
+ log("muxAB: %s\n", log_id(st.muxAB, "--"));
+ log("ffO_lo: %s\n", log_id(st.ffO_lo, "--"));
+ log("ffO_hi: %s\n", log_id(st.ffO_hi, "--"));
#endif
log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@@ -52,42 +53,42 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
return;
}
- if (GetSize(st.sigS) > 32) {
- log(" accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigS), GetSize(st.sigS));
+ if (GetSize(st.sigO) > 33) {
+ log(" adder/accumulator (%s) is too large (%d > 33).\n", log_signal(st.sigO), GetSize(st.sigO));
return;
}
- if (GetSize(st.sigY) > 32) {
- log(" output (%s) is too large (%d > 32).\n", log_signal(st.sigY), GetSize(st.sigY));
+ if (GetSize(st.sigH) > 32) {
+ log(" output (%s) is too large (%d > 32).\n", log_signal(st.sigH), GetSize(st.sigH));
return;
}
- bool mul_signed = st.mul->getParam("\\A_SIGNED").as_bool();
+ Cell *cell = st.mul;
+ if (cell->type == "$mul") {
+ log(" replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
- log(" replacing $mul with SB_MAC16 cell.\n");
-
- Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
- pm.module->swap_names(cell, st.mul);
+ cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
+ pm.module->swap_names(cell, st.mul);
+ }
+ else log_assert(cell->type == "\\SB_MAC16");
// SB_MAC16 Input Interface
-
SigSpec A = st.sigA;
- A.extend_u0(16, mul_signed);
+ log_assert(GetSize(A) == 16);
SigSpec B = st.sigB;
- B.extend_u0(16, mul_signed);
+ log_assert(GetSize(B) == 16);
- SigSpec CD;
- if (st.muxA)
- CD = st.muxA->getPort("\\B");
- if (st.muxB)
- CD = st.muxB->getPort("\\A");
- CD.extend_u0(32, mul_signed);
+ SigSpec CD = st.sigCD;
+ if (CD.empty())
+ CD = RTLIL::Const(0, 32);
+ else
+ log_assert(GetSize(CD) == 32);
cell->setPort("\\A", A);
cell->setPort("\\B", B);
- cell->setPort("\\C", CD.extract(0, 16));
- cell->setPort("\\D", CD.extract(16, 16));
+ cell->setPort("\\C", CD.extract(16, 16));
+ cell->setPort("\\D", CD.extract(0, 16));
cell->setParam("\\A_REG", st.ffA ? State::S1 : State::S0);
cell->setParam("\\B_REG", st.ffB ? State::S1 : State::S0);
@@ -100,7 +101,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setPort("\\IRSTTOP", State::S0);
cell->setPort("\\IRSTBOT", State::S0);
- if (st.clock_vld)
+ if (st.clock != SigBit())
{
cell->setPort("\\CLK", st.clock);
cell->setPort("\\CE", State::S1);
@@ -114,11 +115,13 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.ffB)
log(" ffB:%s", log_id(st.ffB));
- if (st.ffY)
- log(" ffY:%s", log_id(st.ffY));
+ if (st.ffFJKG)
+ log(" ffFJKG:%s", log_id(st.ffFJKG));
- if (st.ffS)
- log(" ffS:%s", log_id(st.ffS));
+ if (st.ffO_lo)
+ log(" ffO_lo:%s", log_id(st.ffO_lo));
+ if (st.ffO_hi)
+ log(" ffO_hi:%s", log_id(st.ffO_hi));
log("\n");
}
@@ -135,21 +138,43 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setPort("\\SIGNEXTOUT", pm.module->addWire(NEW_ID));
cell->setPort("\\CI", State::Sx);
- cell->setPort("\\CO", pm.module->addWire(NEW_ID));
cell->setPort("\\ACCUMCI", State::Sx);
cell->setPort("\\ACCUMCO", pm.module->addWire(NEW_ID));
// SB_MAC16 Output Interface
- SigSpec O = st.ffS ? st.sigS : st.sigY;
+ SigSpec O = st.sigO;
+ int O_width = GetSize(O);
+ if (O_width == 33) {
+ log_assert(st.addAB);
+ // If we have a signed multiply-add, then perform sign extension
+ // TODO: Need to check CD[31:16] is sign extension of CD[15:0]?
+ if (st.addAB->getParam("\\A_SIGNED").as_bool() && st.addAB->getParam("\\B_SIGNED").as_bool())
+ pm.module->connect(O[32], O[31]);
+ else
+ cell->setPort("\\CO", O[32]);
+ O.remove(O_width-1);
+ }
+ else
+ cell->setPort("\\CO", pm.module->addWire(NEW_ID));
+ log_assert(GetSize(O) <= 32);
if (GetSize(O) < 32)
O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
cell->setPort("\\O", O);
+ bool accum = false;
if (st.addAB) {
- log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
+ if (st.addA)
+ accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == st.sigO);
+ else if (st.addB)
+ accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == st.sigO);
+ else log_abort();
+ if (accum)
+ log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
+ else
+ log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
cell->setPort("\\ADDSUBTOP", st.addAB->type == "$add" ? State::S0 : State::S1);
cell->setPort("\\ADDSUBBOT", st.addAB->type == "$add" ? State::S0 : State::S1);
} else {
@@ -177,28 +202,39 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam("\\C_REG", State::S0);
cell->setParam("\\D_REG", State::S0);
- cell->setParam("\\TOP_8x8_MULT_REG", st.ffY ? State::S1 : State::S0);
- cell->setParam("\\BOT_8x8_MULT_REG", st.ffY ? State::S1 : State::S0);
- cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffY ? State::S1 : State::S0);
+ cell->setParam("\\TOP_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0);
+ cell->setParam("\\BOT_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0);
+ cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffFJKG ? State::S1 : State::S0);
cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
- cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : 3, 2));
+ cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO_hi ? 1 : (st.addAB ? 0 : 3), 2));
cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
- cell->setParam("\\TOPADDSUB_UPPERINPUT", State::S0);
+ cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
- cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : 3, 2));
+ cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffO_lo ? 1 : (st.addAB ? 0 : 3), 2));
cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
- cell->setParam("\\BOTADDSUB_UPPERINPUT", State::S0);
+ cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
cell->setParam("\\MODE_8x8", State::S0);
- cell->setParam("\\A_SIGNED", mul_signed ? State::S1 : State::S0);
- cell->setParam("\\B_SIGNED", mul_signed ? State::S1 : State::S0);
+ cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
+ cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
- pm.autoremove(st.mul);
- pm.autoremove(st.ffY);
- pm.autoremove(st.ffS);
+ if (cell != st.mul)
+ pm.autoremove(st.mul);
+ else
+ pm.blacklist(st.mul);
+ pm.autoremove(st.ffFJKG);
+ pm.autoremove(st.addAB);
+ if (st.ffO_lo) {
+ SigSpec O = st.sigO.extract(0,std::min(16,st.ffO_lo->getParam("\\WIDTH").as_int()));
+ st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+ }
+ if (st.ffO_hi) {
+ SigSpec O = st.sigO.extract_end(16);
+ st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+ }
}
struct Ice40DspPass : public Pass {
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 7003092bb..8221cdb69 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -1,87 +1,128 @@
pattern ice40_dsp
state <SigBit> clock
-state <bool> clock_pol clock_vld
-state <SigSpec> sigA sigB sigY sigS
+state <bool> clock_pol
+state <std::set<SigBit>> sigAset sigBset
+state <SigSpec> sigA sigB sigCD sigH sigO sigOused
state <Cell*> addAB muxAB
match mul
- select mul->type.in($mul)
+ select mul->type.in($mul, \SB_MAC16)
select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
- select GetSize(mul->getPort(\Y)) > 10
endmatch
+code sigAset sigBset
+ SigSpec A = port(mul, \A);
+ A.remove_const();
+ sigAset = A.to_sigbit_set();
+ SigSpec B = port(mul, \B);
+ B.remove_const();
+ sigBset = B.to_sigbit_set();
+endcode
+
+code sigH
+ if (mul->type == $mul)
+ sigH = mul->getPort(\Y);
+ else if (mul->type == \SB_MAC16)
+ sigH = mul->getPort(\O);
+ else log_abort();
+ if (GetSize(sigH) <= 10)
+ reject;
+endcode
+
match ffA
+ if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
+ if !sigAset.empty()
select ffA->type.in($dff)
- // select nusers(port(ffA, \Q)) == 2
- index <SigSpec> port(ffA, \Q) === port(mul, \A)
optional
endmatch
-code sigA clock clock_pol clock_vld
+code sigA clock clock_pol
sigA = port(mul, \A);
if (ffA) {
- sigA = port(ffA, \D);
+ auto ffAset = port(ffA, \Q).to_sigbit_set();
+ if (!std::includes(ffAset.begin(), ffAset.end(), sigAset.begin(), sigAset.end()))
+ reject;
+
+ for (auto b : port(ffA, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
clock = port(ffA, \CLK).as_bit();
clock_pol = param(ffA, \CLK_POLARITY).as_bool();
- clock_vld = true;
+
+ sigA.replace(port(ffA, \Q), port(ffA, \D));
}
endcode
match ffB
+ if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
+ if !sigBset.empty()
select ffB->type.in($dff)
- // select nusers(port(ffB, \Q)) == 2
- index <SigSpec> port(ffB, \Q) === port(mul, \B)
optional
endmatch
-code sigB clock clock_pol clock_vld
+code sigB clock clock_pol
sigB = port(mul, \B);
if (ffB) {
- sigB = port(ffB, \D);
+ auto ffBset = port(ffB, \Q).to_sigbit_set();
+ if (!std::includes(ffBset.begin(), ffBset.end(), sigBset.begin(), sigBset.end()))
+ reject;
+
+ for (auto b : port(ffB, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
+
SigBit c = port(ffB, \CLK).as_bit();
bool cp = param(ffB, \CLK_POLARITY).as_bool();
- if (clock_vld && (c != clock || cp != clock_pol))
+ if (clock != SigBit() && (c != clock || cp != clock_pol))
reject;
clock = c;
clock_pol = cp;
- clock_vld = true;
+
+ sigB.replace(port(ffB, \Q), port(ffB, \D));
}
endcode
-match ffY
- select ffY->type.in($dff)
- select nusers(port(ffY, \D)) == 2
- index <SigSpec> port(ffY, \D) === port(mul, \Y)
+match ffFJKG
+ // Ensure pipeline register is not already used
+ if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
+ select ffFJKG->type.in($dff)
+ select nusers(port(ffFJKG, \D)) == 2
+ index <SigSpec> port(ffFJKG, \D) === sigH
optional
endmatch
-code sigY clock clock_pol clock_vld
- sigY = port(mul, \Y);
+code sigH sigO clock clock_pol
+ if (ffFJKG) {
+ sigH = port(ffFJKG, \Q);
+ for (auto b : sigH)
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
- if (ffY) {
- sigY = port(ffY, \Q);
- SigBit c = port(ffY, \CLK).as_bit();
- bool cp = param(ffY, \CLK_POLARITY).as_bool();
+ SigBit c = port(ffFJKG, \CLK).as_bit();
+ bool cp = param(ffFJKG, \CLK_POLARITY).as_bool();
- if (clock_vld && (c != clock || cp != clock_pol))
+ if (clock != SigBit() && (c != clock || cp != clock_pol))
reject;
clock = c;
clock_pol = cp;
- clock_vld = true;
}
+
+ sigO = sigH;
endcode
match addA
select addA->type.in($add)
select nusers(port(addA, \A)) == 2
- index <SigSpec> port(addA, \A) === sigY
+ filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
+ //index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
+ filter port(addA, \A) == sigH.extract(0, param(addA, \A_WIDTH).as_int())
optional
endmatch
@@ -89,75 +130,174 @@ match addB
if !addA
select addB->type.in($add, $sub)
select nusers(port(addB, \B)) == 2
- index <SigSpec> port(addB, \B) === sigY
+ filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
+ //index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
+ filter port(addB, \B) == sigH.extract(0, param(addB, \B_WIDTH).as_int())
optional
endmatch
-code addAB sigS
+code addAB sigCD sigO
+ bool CD_SIGNED = false;
if (addA) {
addAB = addA;
- sigS = port(addA, \B);
+ sigCD = port(addAB, \B);
+ CD_SIGNED = param(addAB, \B_SIGNED).as_bool();
}
if (addB) {
addAB = addB;
- sigS = port(addB, \A);
+ sigCD = port(addAB, \A);
+ CD_SIGNED = param(addAB, \A_SIGNED).as_bool();
}
if (addAB) {
+ if (mul->type == \SB_MAC16) {
+ // Ensure that adder is not used
+ if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
+ param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
+ reject;
+ }
+
int natural_mul_width = GetSize(sigA) + GetSize(sigB);
- int actual_mul_width = GetSize(sigY);
- int actual_acc_width = GetSize(sigS);
+ int actual_mul_width = GetSize(sigH);
+ int actual_acc_width = GetSize(sigCD);
if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
reject;
- if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
+ // If accumulator, check adder width and signedness
+ if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
reject;
+
+ sigO = port(addAB, \Y);
+ sigCD.extend_u0(32, CD_SIGNED);
}
endcode
match muxA
- if addAB
select muxA->type.in($mux)
- select nusers(port(muxA, \A)) == 2
- index <SigSpec> port(muxA, \A) === port(addAB, \Y)
+ index <int> nusers(port(muxA, \A)) === 2
+ index <SigSpec> port(muxA, \A) === sigO
optional
endmatch
match muxB
- if addAB
if !muxA
select muxB->type.in($mux)
- select nusers(port(muxB, \B)) == 2
- index <SigSpec> port(muxB, \B) === port(addAB, \Y)
+ index <int> nusers(port(muxB, \B)) === 2
+ index <SigSpec> port(muxB, \B) === sigO
optional
endmatch
code muxAB
- muxAB = addAB;
if (muxA)
muxAB = muxA;
- if (muxB)
+ else if (muxB)
muxAB = muxB;
endcode
-match ffS
- if muxAB
- select ffS->type.in($dff)
- select nusers(port(ffS, \D)) == 2
- index <SigSpec> port(ffS, \D) === port(muxAB, \Y)
- index <SigSpec> port(ffS, \Q) === sigS
+// Extract the bits of P that actually have a consumer
+// (as opposed to being a dummy)
+code sigOused
+ for (int i = 0; i < GetSize(sigO); i++)
+ if (!sigO[i].wire || nusers(sigO[i]) == 1)
+ sigOused.append(State::Sx);
+ else
+ sigOused.append(sigO[i]);
+endcode
+
+match ffO_lo
+ if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
+ select ffO_lo->type.in($dff)
+ optional
endmatch
-code clock clock_pol clock_vld
- if (ffS) {
- SigBit c = port(ffS, \CLK).as_bit();
- bool cp = param(ffS, \CLK_POLARITY).as_bool();
+code
+ if (ffO_lo) {
+ SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
+ O.remove_const();
+ auto ffO_loSet = port(ffO_lo, \D).to_sigbit_set();
+ auto Oset = O.to_sigbit_set();
+ if (!std::includes(ffO_loSet.begin(), ffO_loSet.end(), Oset.begin(), Oset.end()))
+ reject;
+ }
+endcode
- if (clock_vld && (c != clock || cp != clock_pol))
+match ffO_hi
+ if GetSize(sigOused) > 16
+ if nusers(sigOused.extract_end(16)) == 2
+ select ffO_hi->type.in($dff)
+ optional
+endmatch
+
+code
+ if (ffO_hi) {
+ SigSpec O = sigOused.extract_end(16);
+ O.remove_const();
+ auto ffO_hiSet = port(ffO_hi, \D).to_sigbit_set();
+ auto Oset = O.to_sigbit_set();
+ if (!std::includes(ffO_hiSet.begin(), ffO_hiSet.end(), Oset.begin(), Oset.end()))
reject;
+ }
+endcode
- clock = c;
- clock_pol = cp;
- clock_vld = true;
+code clock clock_pol sigO sigCD
+ if (ffO_lo || ffO_hi) {
+ if (mul->type == \SB_MAC16) {
+ // Ensure that register is not already used
+ if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
+ param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
+ reject;
+
+ // Ensure that OLOADTOP/OLOADBOT is unused or zero
+ if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
+ || (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
+ reject;
+ }
+
+ if (ffO_lo) {
+ for (auto b : port(ffO_lo, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
+
+ SigBit c = port(ffO_lo, \CLK).as_bit();
+ bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
+
+ if (clock != SigBit() && (c != clock || cp != clock_pol))
+ reject;
+
+ clock = c;
+ clock_pol = cp;
+
+ sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
+ }
+
+ if (ffO_hi) {
+ for (auto b : port(ffO_hi, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
+
+ SigBit c = port(ffO_hi, \CLK).as_bit();
+ bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
+
+ if (clock != SigBit() && (c != clock || cp != clock_pol))
+ reject;
+
+ clock = c;
+ clock_pol = cp;
+
+ sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
+ }
+
+ // Loading value into output register is not
+ // supported unless using accumulator
+ if (muxAB) {
+ if (sigCD != sigO)
+ reject;
+ if (muxA)
+ sigCD = port(muxAB, \B);
+ else if (muxB)
+ sigCD = port(muxAB, \A);
+ else log_abort();
+ sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
+ }
}
accept;
endcode
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
new file mode 100644
index 000000000..9291c2dfb
--- /dev/null
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -0,0 +1,243 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+#include "passes/pmgen/xilinx_dsp_pm.h"
+
+void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
+{
+ auto &st = pm.st_xilinx_dsp;
+
+#if 1
+ log("\n");
+ log("ffA: %s\n", log_id(st.ffA, "--"));
+ log("ffAmux: %s\n", log_id(st.ffAmux, "--"));
+ log("ffB: %s\n", log_id(st.ffB, "--"));
+ log("ffBmux: %s\n", log_id(st.ffBmux, "--"));
+ log("dsp: %s\n", log_id(st.dsp, "--"));
+ log("ffM: %s\n", log_id(st.ffM, "--"));
+ log("ffMmux: %s\n", log_id(st.ffMmux, "--"));
+ log("postAdd: %s\n", log_id(st.postAdd, "--"));
+ log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
+ log("ffP: %s\n", log_id(st.ffP, "--"));
+ log("ffPmux: %s\n", log_id(st.ffPmux, "--"));
+#endif
+
+ log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
+
+ Cell *cell = st.dsp;
+ bit_to_driver.insert(std::make_pair(cell->getPort("\\P")[17], cell));
+ SigSpec C = st.sigC;
+ SigSpec P = st.sigP;
+
+ if (st.postAdd) {
+ log(" adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
+
+ SigSpec &opmode = cell->connections_.at("\\OPMODE");
+ if (st.postAddMux) {
+ log_assert(st.ffP);
+ opmode[4] = st.postAddMux->getPort("\\S");
+ pm.autoremove(st.postAddMux);
+ }
+ else if (st.ffP && C == P) {
+ C = SigSpec();
+ opmode[4] = State::S0;
+ }
+ else
+ opmode[4] = State::S1;
+ opmode[6] = State::S0;
+ opmode[5] = State::S1;
+
+ pm.autoremove(st.postAdd);
+ }
+
+ if (st.clock != SigBit())
+ {
+ cell->setPort("\\CLK", st.clock);
+
+ if (st.ffA) {
+ SigSpec A = cell->getPort("\\A");
+ SigSpec D = st.ffA->getPort("\\D");
+ SigSpec Q = pm.sigmap(st.ffA->getPort("\\Q"));
+ A.replace(Q, D);
+ if (st.ffAmux) {
+ SigSpec Y = st.ffAmux->getPort("\\Y");
+ SigSpec AB = st.ffAmux->getPort(st.ffAmuxAB == "\\A" ? "\\B" : "\\A");
+ A.replace(Y, AB);
+ cell->setPort("\\CEA2", st.ffAmux->getPort("\\S"));
+ }
+ else
+ cell->setPort("\\CEA2", State::S1);
+ cell->setPort("\\A", A);
+
+ cell->setParam("\\AREG", 1);
+ }
+ if (st.ffB) {
+ SigSpec B = cell->getPort("\\B");
+ SigSpec D = st.ffB->getPort("\\D");
+ SigSpec Q = st.ffB->getPort("\\Q");
+ B.replace(Q, D);
+ if (st.ffBmux) {
+ SigSpec Y = st.ffBmux->getPort("\\Y");
+ SigSpec AB = st.ffBmux->getPort(st.ffBmuxAB == "\\A" ? "\\B" : "\\A");
+ B.replace(Y, AB);
+ cell->setPort("\\CEB2", st.ffBmux->getPort("\\S"));
+ }
+ else
+ cell->setPort("\\CEB2", State::S1);
+ cell->setPort("\\B", B);
+
+ cell->setParam("\\BREG", 1);
+ }
+ if (st.ffM) {
+ if (st.ffMmux) {
+ cell->setPort("\\CEM", st.ffMmux->getPort("\\S"));
+ pm.autoremove(st.ffMmux);
+ }
+ else
+ cell->setPort("\\CEM", State::S1);
+ SigSpec D = st.ffM->getPort("\\D");
+ SigSpec Q = st.ffM->getPort("\\Q");
+ P.replace(pm.sigmap(D), Q);
+
+ cell->setParam("\\MREG", State::S1);
+ pm.autoremove(st.ffM);
+ }
+ if (st.ffP) {
+ if (st.ffPmux) {
+ cell->setPort("\\CEP", st.ffPmux->getPort("\\S"));
+ st.ffPmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
+ }
+ else
+ cell->setPort("\\CEP", State::S1);
+ SigSpec D = st.ffP->getPort("\\D");
+ SigSpec Q = st.ffP->getPort("\\Q");
+ P.replace(pm.sigmap(D), Q);
+ st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
+
+ cell->setParam("\\PREG", State::S1);
+ }
+
+ log(" clock: %s (%s)", log_signal(st.clock), "posedge");
+
+ if (st.ffA)
+ log(" ffA:%s", log_id(st.ffA));
+
+ if (st.ffB)
+ log(" ffB:%s", log_id(st.ffB));
+
+ if (st.ffM)
+ log(" ffM:%s", log_id(st.ffM));
+
+ if (st.ffP)
+ log(" ffP:%s", log_id(st.ffP));
+
+ log("\n");
+ }
+
+ if (!C.empty()) {
+ if (GetSize(C) < 48)
+ C.extend_u0(48, true);
+ cell->setPort("\\C", C);
+ }
+
+ if (GetSize(P) < 48)
+ P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
+ cell->setPort("\\P", P);
+
+ pm.blacklist(cell);
+}
+
+struct XilinxDspPass : public Pass {
+ XilinxDspPass() : Pass("xilinx_dsp", "Xilinx: pack DSP registers") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" xilinx_dsp [options] [selection]\n");
+ log("\n");
+ log("Pack registers into Xilinx DSPs\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing XILINX_DSP pass (pack DSPs).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ // if (args[argidx] == "-singleton") {
+ // singleton_mode = true;
+ // continue;
+ // }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules()) {
+ xilinx_dsp_pm pm(module, module->selected_cells());
+ dict<SigBit, Cell*> bit_to_driver;
+ auto f = [&bit_to_driver](xilinx_dsp_pm &pm){ pack_xilinx_dsp(bit_to_driver, pm); };
+ pm.run_xilinx_dsp(f);
+
+ // Look for ability to convert C input from another DSP into PCIN
+ // NB: Needs to be done after pattern matcher has folded all
+ // $add cells into the DSP
+ for (auto cell : module->cells()) {
+ if (cell->type != "\\DSP48E1")
+ continue;
+ SigSpec &opmode = cell->connections_.at("\\OPMODE");
+ if (opmode.extract(4,3) != Const::from_string("011"))
+ continue;
+ SigSpec C = pm.sigmap(cell->getPort("\\C"));
+ if (C.has_const())
+ continue;
+ auto it = bit_to_driver.find(C[0]);
+ if (it == bit_to_driver.end())
+ continue;
+ auto driver = it->second;
+
+ // Unextend C
+ int i;
+ for (i = GetSize(C)-1; i > 0; i--)
+ if (C[i] != C[i-1])
+ break;
+ if (i > 48-17)
+ continue;
+ if (driver->getPort("\\P").extract(17, i) == C.extract(0, i)) {
+ cell->setPort("\\C", Const(0, 48));
+ Wire *cascade = module->addWire(NEW_ID, 48);
+ driver->setPort("\\PCOUT", cascade);
+ cell->setPort("\\PCIN", cascade);
+ opmode[6] = State::S1;
+ opmode[5] = State::S0;
+ opmode[4] = State::S1;
+ bit_to_driver.erase(it);
+ }
+ }
+ }
+ }
+} XilinxDspPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
new file mode 100644
index 000000000..fa490146c
--- /dev/null
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -0,0 +1,273 @@
+pattern xilinx_dsp
+
+state <SigBit> clock
+state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP
+state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
+
+match dsp
+ select dsp->type.in(\DSP48E1)
+endmatch
+
+code sigA sigffAmux sigB sigffBmux sigM
+ sigA = port(dsp, \A);
+ int i;
+ for (i = GetSize(sigA)-1; i > 0; i--)
+ if (sigA[i] != sigA[i-1])
+ break;
+ // Do not remove non-const sign bit
+ if (sigA[i].wire)
+ ++i;
+ sigA.remove(i, GetSize(sigA)-i);
+ sigB = port(dsp, \B);
+ for (i = GetSize(sigB)-1; i > 0; i--)
+ if (sigB[i] != sigB[i-1])
+ break;
+ // Do not remove non-const sign bit
+ if (sigB[i].wire)
+ ++i;
+ sigB.remove(i, GetSize(sigB)-i);
+
+ SigSpec P = port(dsp, \P);
+ // Only care about those bits that are used
+ for (i = 0; i < GetSize(P); i++) {
+ if (nusers(P[i]) <= 1)
+ break;
+ sigM.append(P[i]);
+ }
+ log_assert(nusers(P.extract_end(i)) <= 1);
+ //if (GetSize(sigM) <= 10)
+ // reject;
+endcode
+
+match ffA
+ if param(dsp, \AREG).as_int() == 0
+ select ffA->type.in($dff)
+ // DSP48E1 does not support clock inversion
+ select param(ffA, \CLK_POLARITY).as_bool()
+ filter GetSize(port(ffA, \Q)) >= GetSize(sigA)
+ slice offset GetSize(port(ffA, \Q))
+ filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q)) && port(ffA, \Q).extract(offset, GetSize(sigA)) == sigA
+ optional
+endmatch
+
+code sigA sigffAmux clock
+ if (ffA) {
+ for (auto b : port(ffA, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
+
+ clock = port(ffA, \CLK).as_bit();
+
+ sigffAmux = sigA;
+ sigA.replace(port(ffA, \Q), port(ffA, \D));
+ }
+endcode
+
+match ffAmux
+ if ffA
+ select ffAmux->type.in($mux)
+ filter GetSize(port(ffAmux, \Y)) >= GetSize(sigA)
+ slice offset GetSize(port(ffAmux, \Y))
+ filter offset+GetSize(sigA) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, \Y).extract(offset, GetSize(sigA)) == sigA
+ choice <IdString> AB {\A, \B}
+ filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, AB).extract(offset, GetSize(sigffAmux)) == sigffAmux
+ set ffAmuxAB AB
+ semioptional
+endmatch
+
+match ffB
+ if param(dsp, \BREG).as_int() == 0
+ select ffB->type.in($dff)
+ // DSP48E1 does not support clock inversion
+ select param(ffB, \CLK_POLARITY).as_bool()
+ filter GetSize(port(ffB, \Q)) >= GetSize(sigB)
+ slice offset GetSize(port(ffB, \Q))
+ filter offset+GetSize(sigB) <= GetSize(port(ffB, \Q)) && port(ffB, \Q).extract(offset, GetSize(sigB)) == sigB
+ optional
+endmatch
+
+code sigB sigffBmux clock
+ if (ffB) {
+ for (auto b : port(ffB, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
+
+ SigBit c = port(ffB, \CLK).as_bit();
+
+ if (clock != SigBit() && c != clock)
+ reject;
+
+ clock = c;
+
+ sigffBmux = sigB;
+ sigB.replace(port(ffB, \Q), port(ffB, \D));
+ }
+endcode
+
+match ffBmux
+ if ffB
+ select ffBmux->type.in($mux)
+ filter GetSize(port(ffBmux, \Y)) >= GetSize(sigB)
+ slice offset GetSize(port(ffBmux, \Y))
+ filter offset+GetSize(sigB) <= GetSize(port(ffBmux, \Y)) && port(ffBmux, \Y).extract(offset, GetSize(sigB)) == sigB
+ choice <IdString> AB {\A, \B}
+ filter offset+GetSize(sigffBmux) <= GetSize(port(ffBmux, \Y)) && port(ffBmux, AB).extract(offset, GetSize(sigffBmux)) == sigffBmux
+ set ffBmuxAB AB
+ semioptional
+endmatch
+
+match ffMmux
+ select ffMmux->type.in($mux)
+ select nusers(port(ffMmux, \Y)) == 2
+ filter GetSize(port(ffMmux, \Y)) <= GetSize(sigM)
+ choice <IdString> AB {\A, \B}
+ filter port(ffMmux, AB) == sigM.extract(0, GetSize(port(ffMmux, \Y)))
+ filter nusers(sigM.extract_end(GetSize(port(ffMmux, AB)))) <= 1
+ set ffMmuxAB AB
+ optional
+endmatch
+
+code sigM
+ if (ffMmux)
+ sigM = port(ffMmux, \Y);
+endcode
+
+match ffM
+ if param(dsp, \MREG).as_int() == 0
+ select ffM->type.in($dff)
+ // DSP48E1 does not support clock inversion
+ select param(ffM, \CLK_POLARITY).as_bool()
+ select nusers(port(ffM, \D)) == 2
+ filter GetSize(port(ffM, \D)) <= GetSize(sigM)
+ filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D)))
+ filter nusers(sigM.extract_end(GetSize(port(ffM, \D)))) <= 1
+ // Check ffMmux (when present) is a $dff enable mux
+ filter !ffMmux || port(ffM, \Q) == port(ffMmux, ffMmuxAB == \A ? \B : \A)
+ optional
+endmatch
+
+code clock sigM sigP
+ if (ffM) {
+ sigM = port(ffM, \Q);
+
+ for (auto b : sigM)
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
+
+ SigBit c = port(ffM, \CLK).as_bit();
+
+ if (clock != SigBit() && c != clock)
+ reject;
+
+ clock = c;
+ }
+ // Cannot have ffMmux enable mux without ffM
+ else if (ffMmux)
+ reject;
+
+ sigP = sigM;
+endcode
+
+match postAdd
+ // Ensure that Z mux is not already used
+ if port(dsp, \OPMODE).extract(4,3).is_fully_zero()
+
+ select postAdd->type.in($add)
+ choice <IdString> AB {\A, \B}
+ select nusers(port(postAdd, AB)) <= 3
+ filter ffMmux || nusers(port(postAdd, AB)) == 2
+ filter !ffMmux || nusers(port(postAdd, AB)) == 3
+ filter GetSize(port(postAdd, AB)) <= GetSize(sigP)
+ filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB)))
+ filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1
+ set postAddAB AB
+ optional
+endmatch
+
+code sigC sigP
+ if (postAdd) {
+ sigC = port(postAdd, postAddAB == \A ? \B : \A);
+
+ // TODO for DSP48E1, which will have sign extended inputs/outputs
+ //int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B));
+ //int actual_mul_width = GetSize(sigP);
+ //int actual_acc_width = GetSize(sigC);
+
+ //if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
+ // reject;
+ //if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(postAdd, \A_SIGNED).as_bool()))
+ // reject;
+
+ sigP = port(postAdd, \Y);
+ }
+endcode
+
+match ffPmux
+ select ffPmux->type.in($mux)
+ select nusers(port(ffPmux, \Y)) == 2
+ filter GetSize(port(ffPmux, \Y)) <= GetSize(sigP)
+ choice <IdString> AB {\A, \B}
+ filter port(ffPmux, AB) == sigP.extract(0, GetSize(port(ffPmux, \Y)))
+ filter nusers(sigP.extract_end(GetSize(port(ffPmux, AB)))) <= 1
+ set ffPmuxAB AB
+ optional
+endmatch
+
+code sigP
+ if (ffPmux)
+ sigP.replace(port(ffPmux, ffPmuxAB), port(ffPmux, \Y));
+endcode
+
+match ffP
+ if param(dsp, \PREG).as_int() == 0
+ select ffP->type.in($dff)
+ // DSP48E1 does not support clock inversion
+ select param(ffP, \CLK_POLARITY).as_bool()
+ filter GetSize(port(ffP, \D)) >= GetSize(sigP)
+ slice offset GetSize(port(ffP, \D))
+ filter offset+GetSize(sigP) <= GetSize(port(ffP, \D)) && port(ffP, \D).extract(offset, GetSize(sigP)) == sigP
+ // Check ffPmux (when present) is a $dff enable mux
+ filter !ffPmux || port(ffP, \Q) == port(ffPmux, ffPmuxAB == \A ? \B : \A)
+ optional
+endmatch
+
+code ffP sigP clock
+ if (ffP) {
+ for (auto b : port(ffP, \Q))
+ if (b.wire->get_bool_attribute(\keep))
+ reject;
+
+ SigBit c = port(ffP, \CLK).as_bit();
+
+ if (clock != SigBit() && c != clock)
+ reject;
+
+ clock = c;
+
+ sigP.replace(port(ffP, \D), port(ffP, \Q));
+ }
+ // Cannot have ffPmux enable mux without ffP
+ else if (ffPmux)
+ reject;
+endcode
+
+match postAddMux
+ if postAdd
+ if ffP
+ select postAddMux->type.in($mux)
+ select nusers(port(postAddMux, \Y)) == 2
+ choice <IdString> AB {\A, \B}
+ index <SigSpec> port(postAddMux, AB) === sigP
+ index <SigSpec> port(postAddMux, \Y) === sigC
+ set postAddMuxAB AB
+ optional
+endmatch
+
+code sigC
+ if (postAddMux)
+ sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
+endcode
+
+code
+ accept;
+endcode
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 6fdf987f0..7eac08d17 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -76,8 +76,7 @@ inline std::string remap_name(RTLIL::IdString abc_name)
return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
}
-void handle_loops(RTLIL::Design *design,
- const dict<IdString,pool<IdString>> &scc_break_inputs)
+void handle_loops(RTLIL::Design *design)
{
Pass::call(design, "scc -set_attr abc_scc_id {}");
@@ -114,30 +113,6 @@ void handle_loops(RTLIL::Design *design,
}
cell->attributes.erase(it);
}
-
- auto jt = scc_break_inputs.find(cell->type);
- if (jt != scc_break_inputs.end())
- for (auto port_name : jt->second) {
- RTLIL::SigSpec sig;
- auto &rhs = cell->connections_.at(port_name);
- for (auto b : rhs) {
- Wire *w = b.wire;
- if (!w) continue;
- w->port_output = true;
- w->set_bool_attribute(ID(abc_scc_break));
- w = module->wire(stringf("%s.abci", w->name.c_str()));
- if (!w) {
- w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
- w->port_input = true;
- }
- else {
- log_assert(b.offset < GetSize(w));
- log_assert(w->port_input);
- }
- sig.append(RTLIL::SigBit(w, b.offset));
- }
- rhs = sig;
- }
}
module->fixup_ports();
@@ -272,8 +247,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
bool show_tempdir, std::string box_file, std::string lut_file,
- std::string wire_delay, const dict<int,IdString> &box_lookup,
- const dict<IdString,pool<IdString>> &scc_break_inputs
+ std::string wire_delay, const dict<int,IdString> &box_lookup
)
{
module = current_module;
@@ -413,7 +387,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
- handle_loops(design, scc_break_inputs);
+ handle_loops(design);
Pass::call(design, "aigmap");
@@ -1050,9 +1024,6 @@ struct Abc9Pass : public Pass {
}
if (arg == "-box" && argidx+1 < args.size()) {
box_file = args[++argidx];
- rewrite_filename(box_file);
- if (!box_file.empty() && !is_absolute_path(box_file))
- box_file = std::string(pwd) + "/" + box_file;
continue;
}
if (arg == "-W" && argidx+1 < args.size()) {
@@ -1063,8 +1034,15 @@ struct Abc9Pass : public Pass {
}
extra_args(args, argidx, design);
+ // ABC expects a box file for XAIG
+ if (box_file.empty())
+ box_file = "+/dummy.box";
+
+ rewrite_filename(box_file);
+ if (!box_file.empty() && !is_absolute_path(box_file))
+ box_file = std::string(pwd) + "/" + box_file;
+
dict<int,IdString> box_lookup;
- dict<IdString,pool<IdString>> scc_break_inputs;
for (auto m : design->modules()) {
auto it = m->attributes.find(ID(abc_box_id));
if (it == m->attributes.end())
@@ -1082,17 +1060,13 @@ struct Abc9Pass : public Pass {
for (auto p : m->ports) {
auto w = m->wire(p);
log_assert(w);
- if (w->port_input) {
- if (w->attributes.count(ID(abc_scc_break)))
- scc_break_inputs[m->name].insert(p);
- if (w->attributes.count(ID(abc_carry))) {
+ if (w->attributes.count(ID(abc_carry))) {
+ if (w->port_input) {
if (carry_in)
log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
carry_in = w;
}
- }
- if (w->port_output) {
- if (w->attributes.count(ID(abc_carry))) {
+ else if (w->port_output) {
if (carry_out)
log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
carry_out = w;
@@ -1144,7 +1118,7 @@ struct Abc9Pass : public Pass {
if (!dff_mode || !clk_str.empty()) {
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
delay_target, lutin_shared, fast_mode, show_tempdir,
- box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
+ box_file, lut_file, wire_delay, box_lookup);
continue;
}
@@ -1290,7 +1264,7 @@ struct Abc9Pass : public Pass {
en_sig = assign_map(std::get<3>(it.first));
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
- box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
+ box_file, lut_file, wire_delay, box_lookup);
assign_map.set(mod);
}
}
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index c4496f76f..5ce1bf7d6 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -205,20 +205,38 @@ struct TechmapWorker
}
std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
+ dict<Wire*, IdString> temp_renamed_wires;
for (auto &it : tpl->wires_) {
if (it.second->port_id > 0)
positional_ports[stringf("$%d", it.second->port_id)] = it.first;
IdString w_name = it.second->name;
apply_prefix(cell->name, w_name);
- RTLIL::Wire *w = module->addWire(w_name, it.second);
- w->port_input = false;
- w->port_output = false;
- w->port_id = 0;
- if (it.second->get_bool_attribute(ID(_techmap_special_)))
- w->attributes.clear();
- if (w->attributes.count(ID(src)))
- w->add_strpool_attribute(ID(src), extra_src_attrs);
+ RTLIL::Wire *w = module->wire(w_name);
+ if (w != nullptr) {
+ if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) {
+ temp_renamed_wires[w] = w->name;
+ module->rename(w, NEW_ID);
+ w = nullptr;
+ } else {
+ w->attributes.erase(ID(hierconn));
+ if (GetSize(w) < GetSize(it.second)) {
+ log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
+ log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
+ w->width = GetSize(it.second);
+ }
+ }
+ }
+ if (w == nullptr) {
+ w = module->addWire(w_name, it.second);
+ w->port_input = false;
+ w->port_output = false;
+ w->port_id = 0;
+ if (it.second->get_bool_attribute(ID(_techmap_special_)))
+ w->attributes.clear();
+ if (w->attributes.count(ID(src)))
+ w->add_strpool_attribute(ID(src), extra_src_attrs);
+ }
design->select(module, w);
}
@@ -380,6 +398,16 @@ struct TechmapWorker
}
module->remove(cell);
+
+ for (auto &it : temp_renamed_wires)
+ {
+ Wire *w = it.first;
+ IdString name = it.second;
+ IdString altname = module->uniquify(name);
+ Wire *other_w = module->wire(name);
+ module->rename(other_w, altname);
+ module->rename(w, name);
+ }
}
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index bfb1d6642..7f11e54f3 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -348,6 +348,11 @@ struct TestAutotbBackend : public Backend {
log(" -n <int>\n");
log(" number of iterations the test bench should run (default = 1000)\n");
log("\n");
+ log(" -seed <int>\n");
+ log(" seed used for pseudo-random number generation (default = 0).\n");
+ log(" a value of 0 will cause an arbitrary seed to be chosen, based on\n");
+ log(" the current system time.\n");
+ log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-29 10:00:07 +0000