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-rw-r--r--passes/techmap/abc.cc26
-rw-r--r--passes/techmap/abc9.cc8
-rw-r--r--passes/techmap/aigmap.cc2
-rw-r--r--passes/techmap/deminout.cc2
-rw-r--r--passes/techmap/dff2dffe.cc6
-rw-r--r--passes/techmap/muxcover.cc10
-rw-r--r--passes/techmap/simplemap.cc4
7 files changed, 29 insertions, 29 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index c0cfe2f36..7cb784505 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -166,7 +166,7 @@ void mark_port(RTLIL::SigSpec sig)
void extract_cell(RTLIL::Cell *cell, bool keepff)
{
- if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
+ if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
if (clk_polarity != (cell->type == "$_DFF_P_"))
return;
@@ -177,11 +177,11 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
goto matching_dff;
}
- if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
+ if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
{
- if (clk_polarity != (cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"))
+ if (clk_polarity != cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"))
return;
- if (en_polarity != (cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"))
+ if (en_polarity != cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"))
return;
if (clk_sig != assign_map(cell->getPort("\\C")))
return;
@@ -343,7 +343,7 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
abc_sname.erase(0, 5);
if (std::isdigit(abc_sname.at(0)))
{
- int sid = std::stoi(abc_sname);
+ int sid = std::atoi(abc_sname.c_str());
size_t postfix_start = abc_sname.find_first_not_of("0123456789");
std::string postfix = postfix_start != std::string::npos ? abc_sname.substr(postfix_start) : "";
@@ -1562,10 +1562,10 @@ struct AbcPass : public Pass {
size_t pos = arg.find_first_of(':');
int lut_mode = 0, lut_mode2 = 0;
if (pos != string::npos) {
- lut_mode = atoi(arg.substr(0, pos).c_str());
- lut_mode2 = atoi(arg.substr(pos+1).c_str());
+ lut_mode = std::atoi(arg.substr(0, pos).c_str());
+ lut_mode2 = std::atoi(arg.substr(pos+1).c_str());
} else {
- lut_mode = atoi(arg.c_str());
+ lut_mode = std::atoi(arg.c_str());
lut_mode2 = lut_mode;
}
lut_costs.clear();
@@ -1584,7 +1584,7 @@ struct AbcPass : public Pass {
else if (GetSize(parts) == 1)
lut_costs.push_back(atoi(parts.at(0).c_str()));
else if (GetSize(parts) == 2)
- while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
+ while (GetSize(lut_costs) < std::atoi(parts.at(0).c_str()))
lut_costs.push_back(atoi(parts.at(1).c_str()));
else
log_cmd_error("Invalid -luts syntax.\n");
@@ -1822,15 +1822,15 @@ struct AbcPass : public Pass {
}
}
- if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
+ if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
}
else
- if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
+ if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_" "$_DFFE_PN_", "$_DFFE_PP_"))
{
- bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
- bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
+ bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
+ bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
}
else
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 658bb1225..34919cf07 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1137,15 +1137,15 @@ struct Abc9Pass : public Pass {
}
}
- if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
+ if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
}
else
- if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
+ if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
{
- bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
- bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
+ bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
+ bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
}
else
diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc
index 35df2ff79..2423676cb 100644
--- a/passes/techmap/aigmap.cc
+++ b/passes/techmap/aigmap.cc
@@ -66,7 +66,7 @@ struct AigmapPass : public Pass {
{
Aig aig(cell);
- if (cell->type == "$_AND_" || cell->type == "$_NOT_")
+ if (cell->type.in("$_AND_", "$_NOT_"))
aig.name.clear();
if (nand_mode && cell->type == "$_NAND_")
diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
index 47d0ff416..142d12bdc 100644
--- a/passes/techmap/deminout.cc
+++ b/passes/techmap/deminout.cc
@@ -85,7 +85,7 @@ struct DeminoutPass : public Pass {
if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf"))
{
- bool tribuf = (cell->type == "$_TBUF_" || cell->type == "$tribuf");
+ bool tribuf = cell->type.in("$_TBUF_", "$tribuf");
if (!tribuf) {
for (auto &c : cell->connections()) {
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 7e1040963..8e947b4dc 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -52,13 +52,13 @@ struct Dff2dffeWorker
}
for (auto cell : module->cells()) {
- if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") {
+ if (cell->type.in("$mux", "$pmux", "$_MUX_")) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i);
}
if (direct_dict.empty()) {
- if (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
+ if (cell->type.in("$dff", "$_DFF_N_", "$_DFF_P_"))
dff_cells.push_back(cell);
} else {
if (direct_dict.count(cell->type))
@@ -304,7 +304,7 @@ struct Dff2dffePass : public Pass {
}
if (args[argidx] == "-unmap-mince" && argidx + 1 < args.size()) {
unmap_mode = true;
- min_ce_use = std::stoi(args[++argidx]);
+ min_ce_use = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-direct" && argidx + 2 < args.size()) {
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index d53378a29..45987392e 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -676,14 +676,14 @@ struct MuxcoverPass : public Pass {
{
const auto &arg = args[argidx];
if (arg.size() >= 6 && arg.substr(0,6) == "-mux2=") {
- cost_mux2 = std::stoi(arg.substr(6));
+ cost_mux2 = atoi(arg.substr(6).c_str());
continue;
}
if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") {
use_mux4 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
- cost_mux4 = std::stoi(arg.substr(6));
+ cost_mux4 = atoi(arg.substr(6).c_str());
}
continue;
}
@@ -691,7 +691,7 @@ struct MuxcoverPass : public Pass {
use_mux8 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
- cost_mux8 = std::stoi(arg.substr(6));
+ cost_mux8 = atoi(arg.substr(6).c_str());
}
continue;
}
@@ -699,12 +699,12 @@ struct MuxcoverPass : public Pass {
use_mux16 = true;
if (arg.size() > 6) {
if (arg[6] != '=') break;
- cost_mux16 = std::stoi(arg.substr(7));
+ cost_mux16 = atoi(arg.substr(7).c_str());
}
continue;
}
if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") {
- cost_dmux = std::stoi(arg.substr(6));
+ cost_dmux = atoi(arg.substr(6).c_str());
continue;
}
if (arg == "-nodecode") {
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index f3da80c66..2eaba1b09 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -185,7 +185,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
}
if (sig.size() == 0)
- sig = RTLIL::SigSpec(0, 1);
+ sig = State::S0;
}
void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
@@ -245,7 +245,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
- bool is_ne = cell->type == "$ne" || cell->type == "$nex";
+ bool is_ne = cell->type.in("$ne", "$nex");
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-14 21:05:33 +0000