diff options
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/Makefile.inc | 2 | ||||
| -rw-r--r-- | passes/techmap/dff2dffe.cc | 414 | ||||
| -rw-r--r-- | passes/techmap/dff2dffs.cc | 165 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 59 |
4 files changed, 54 insertions, 586 deletions
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 5a4d84f94..035699603 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -27,7 +27,6 @@ OBJS += passes/techmap/extract_fa.o OBJS += passes/techmap/extract_counter.o OBJS += passes/techmap/extract_reduce.o OBJS += passes/techmap/alumacc.o -OBJS += passes/techmap/dff2dffe.o OBJS += passes/techmap/dffinit.o OBJS += passes/techmap/pmuxtree.o OBJS += passes/techmap/muxcover.o @@ -42,7 +41,6 @@ OBJS += passes/techmap/attrmvcp.o OBJS += passes/techmap/attrmap.o OBJS += passes/techmap/zinit.o OBJS += passes/techmap/dfflegalize.o -OBJS += passes/techmap/dff2dffs.o OBJS += passes/techmap/dffunmap.o OBJS += passes/techmap/flowmap.o OBJS += passes/techmap/extractinv.o diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc deleted file mode 100644 index 62ee3fea6..000000000 --- a/passes/techmap/dff2dffe.cc +++ /dev/null @@ -1,414 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" -#include "kernel/celltypes.h" -#include "passes/techmap/simplemap.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct Dff2dffeWorker -{ - const dict<IdString, IdString> &direct_dict; - - RTLIL::Module *module; - SigMap sigmap; - CellTypes ct; - - typedef std::pair<RTLIL::Cell*, int> cell_int_t; - std::map<RTLIL::SigBit, cell_int_t> bit2mux; - std::vector<RTLIL::Cell*> dff_cells; - std::map<RTLIL::SigBit, int> bitusers; - - typedef std::map<RTLIL::SigBit, bool> pattern_t; - typedef std::set<pattern_t> patterns_t; - - - Dff2dffeWorker(RTLIL::Module *module, const dict<IdString, IdString> &direct_dict) : - direct_dict(direct_dict), module(module), sigmap(module), ct(module->design) - { - for (auto wire : module->wires()) { - if (wire->port_output) - for (auto bit : sigmap(wire)) - bitusers[bit]++; - } - - for (auto cell : module->cells()) { - if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) { - RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); - for (int i = 0; i < GetSize(sig_y); i++) - bit2mux[sig_y[i]] = cell_int_t(cell, i); - } - if (direct_dict.empty()) { - if (cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) - dff_cells.push_back(cell); - } else { - if (direct_dict.count(cell->type)) - dff_cells.push_back(cell); - } - for (auto conn : cell->connections()) { - if (ct.cell_output(cell->type, conn.first)) - continue; - for (auto bit : sigmap(conn.second)) - bitusers[bit]++; - } - } - } - - patterns_t find_muxtree_feedback_patterns(RTLIL::SigBit d, RTLIL::SigBit q, pattern_t path) - { - patterns_t ret; - - if (d == q) { - ret.insert(path); - return ret; - } - - if (bit2mux.count(d) == 0 || bitusers[d] > 1) - return ret; - - cell_int_t mux_cell_int = bit2mux.at(d); - RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort(ID::A)); - RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort(ID::B)); - RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID::S)); - int width = GetSize(sig_a), index = mux_cell_int.second; - - for (int i = 0; i < GetSize(sig_s); i++) - if (path.count(sig_s[i]) && path.at(sig_s[i])) - { - ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path); - - if (sig_b[i*width + index] == q) { - RTLIL::SigSpec s = mux_cell_int.first->getPort(ID::B); - s[i*width + index] = RTLIL::Sx; - mux_cell_int.first->setPort(ID::B, s); - } - - return ret; - } - - pattern_t path_else = path; - - for (int i = 0; i < GetSize(sig_s); i++) - { - if (path.count(sig_s[i])) - continue; - - pattern_t path_this = path; - path_else[sig_s[i]] = false; - path_this[sig_s[i]] = true; - - for (auto &pat : find_muxtree_feedback_patterns(sig_b[i*width + index], q, path_this)) - ret.insert(pat); - - if (sig_b[i*width + index] == q) { - RTLIL::SigSpec s = mux_cell_int.first->getPort(ID::B); - s[i*width + index] = RTLIL::Sx; - mux_cell_int.first->setPort(ID::B, s); - } - } - - for (auto &pat : find_muxtree_feedback_patterns(sig_a[index], q, path_else)) - ret.insert(pat); - - if (sig_a[index] == q) { - RTLIL::SigSpec s = mux_cell_int.first->getPort(ID::A); - s[index] = RTLIL::Sx; - mux_cell_int.first->setPort(ID::A, s); - } - - return ret; - } - - void simplify_patterns(patterns_t&) - { - // TBD - } - - RTLIL::SigSpec make_patterns_logic(patterns_t patterns, bool make_gates) - { - RTLIL::SigSpec or_input; - - for (auto pat : patterns) - { - RTLIL::SigSpec s1, s2; - for (auto it : pat) { - s1.append(it.first); - s2.append(it.second); - } - - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y); - - if (make_gates) { - simplemap(module, c); - module->remove(c); - } - - or_input.append(y); - } - - if (GetSize(or_input) == 0) - return State::S1; - - if (GetSize(or_input) == 1) - return or_input; - - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y); - - if (make_gates) { - simplemap(module, c); - module->remove(c); - } - - return y; - } - - void handle_dff_cell(RTLIL::Cell *dff_cell) - { - RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort(ID::D)); - RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort(ID::Q)); - - std::map<patterns_t, std::set<int>> grouped_patterns; - std::set<int> remaining_indices; - - for (int i = 0 ; i < GetSize(sig_d); i++) { - patterns_t patterns = find_muxtree_feedback_patterns(sig_d[i], sig_q[i], pattern_t()); - if (!patterns.empty()) { - simplify_patterns(patterns); - grouped_patterns[patterns].insert(i); - } else - remaining_indices.insert(i); - } - - for (auto &it : grouped_patterns) { - RTLIL::SigSpec new_sig_d, new_sig_q; - for (int i : it.second) { - new_sig_d.append(sig_d[i]); - new_sig_q.append(sig_q[i]); - } - if (!direct_dict.empty()) { - log(" converting %s cell %s to %s for %s -> %s.\n", log_id(dff_cell->type), log_id(dff_cell), log_id(direct_dict.at(dff_cell->type)), log_signal(new_sig_d), log_signal(new_sig_q)); - dff_cell->setPort(ID::E, make_patterns_logic(it.first, true)); - dff_cell->type = direct_dict.at(dff_cell->type); - } else - if (dff_cell->type == ID($dff)) { - RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort(ID::CLK), make_patterns_logic(it.first, false), - new_sig_d, new_sig_q, dff_cell->getParam(ID::CLK_POLARITY).as_bool(), true); - log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q)); - } else { - RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort(ID::C), make_patterns_logic(it.first, true), - new_sig_d, new_sig_q, dff_cell->type == ID($_DFF_P_), true); - log(" created %s cell %s for %s -> %s.\n", log_id(new_cell->type), log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q)); - } - } - - if (!direct_dict.empty()) - return; - - if (remaining_indices.empty()) { - log(" removing now obsolete cell %s.\n", log_id(dff_cell)); - module->remove(dff_cell); - } else if (GetSize(remaining_indices) != GetSize(sig_d)) { - log(" removing %d now obsolete bits from cell %s.\n", GetSize(sig_d) - GetSize(remaining_indices), log_id(dff_cell)); - RTLIL::SigSpec new_sig_d, new_sig_q; - for (int i : remaining_indices) { - new_sig_d.append(sig_d[i]); - new_sig_q.append(sig_q[i]); - } - dff_cell->setPort(ID::D, new_sig_d); - dff_cell->setPort(ID::Q, new_sig_q); - dff_cell->setParam(ID::WIDTH, GetSize(remaining_indices)); - } - } - - void run() - { - log("Transforming FF to FF+Enable cells in module %s:\n", log_id(module)); - for (auto dff_cell : dff_cells) { - // log("Handling candidate %s:\n", log_id(dff_cell)); - handle_dff_cell(dff_cell); - } - } -}; - -struct Dff2dffePass : public Pass { - Dff2dffePass() : Pass("dff2dffe", "transform $dff cells to $dffe cells") { } - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" dff2dffe [options] [selection]\n"); - log("\n"); - log("This pass transforms $dff cells driven by a tree of multiplexers with one or\n"); - log("more feedback paths to $dffe cells. It also works on gate-level cells such as\n"); - log("$_DFF_P_, $_DFF_N_ and $_MUX_.\n"); - log("\n"); - log(" -unmap\n"); - log(" operate in the opposite direction: replace $dffe cells with combinations\n"); - log(" of $dff and $mux cells. the options below are ignored in unmap mode.\n"); - log("\n"); - log(" -unmap-mince N\n"); - log(" Same as -unmap but only unmap $dffe where the clock enable port\n"); - log(" signal is used by less $dffe than the specified number\n"); - log("\n"); - log(" -direct <internal_gate_type> <external_gate_type>\n"); - log(" map directly to external gate type. <internal_gate_type> can\n"); - log(" be any internal gate-level FF cell (except $_DFFE_??_). the\n"); - log(" <external_gate_type> is the cell type name for a cell with an\n"); - log(" identical interface to the <internal_gate_type>, except it\n"); - log(" also has an high-active enable port 'E'.\n"); - log(" Usually <external_gate_type> is an intermediate cell type\n"); - log(" that is then translated to the final type using 'techmap'.\n"); - log("\n"); - log(" -direct-match <pattern>\n"); - log(" like -direct for all DFF cell types matching the expression.\n"); - log(" this will use $_DFFE_* as <external_gate_type> matching the\n"); - log(" internal gate type $_DFF_*_, and $_SDFFE_* for those matching\n"); - log(" $_SDFF_*_, except for $_DFF_[NP]_, which is converted to \n"); - log(" $_DFFE_[NP]_.\n"); - log("\n"); - } - void execute(std::vector<std::string> args, RTLIL::Design *design) override - { - log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n"); - - bool unmap_mode = false; - int min_ce_use = -1; - dict<IdString, IdString> direct_dict; - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-unmap") { - unmap_mode = true; - continue; - } - if (args[argidx] == "-unmap-mince" && argidx + 1 < args.size()) { - unmap_mode = true; - min_ce_use = atoi(args[++argidx].c_str()); - continue; - } - if (args[argidx] == "-direct" && argidx + 2 < args.size()) { - string direct_from = RTLIL::escape_id(args[++argidx]); - string direct_to = RTLIL::escape_id(args[++argidx]); - direct_dict[direct_from] = direct_to; - continue; - } - if (args[argidx] == "-direct-match" && argidx + 1 < args.size()) { - bool found_match = false; - const char *pattern = args[++argidx].c_str(); - if (patmatch(pattern, "$_DFF_P_" )) found_match = true, direct_dict[ID($_DFF_P_) ] = ID($_DFFE_PP_); - if (patmatch(pattern, "$_DFF_N_" )) found_match = true, direct_dict[ID($_DFF_N_) ] = ID($_DFFE_NP_); - if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict[ID($_DFF_NN0_)] = ID($_DFFE_NN0P_); - if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict[ID($_DFF_NN1_)] = ID($_DFFE_NN1P_); - if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict[ID($_DFF_NP0_)] = ID($_DFFE_NP0P_); - if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict[ID($_DFF_NP1_)] = ID($_DFFE_NP1P_); - if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict[ID($_DFF_PN0_)] = ID($_DFFE_PN0P_); - if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict[ID($_DFF_PN1_)] = ID($_DFFE_PN1P_); - if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict[ID($_DFF_PP0_)] = ID($_DFFE_PP0P_); - if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict[ID($_DFF_PP1_)] = ID($_DFFE_PP1P_); - - if (patmatch(pattern, "$_SDFF_NN0_")) found_match = true, direct_dict[ID($_SDFF_NN0_)] = ID($_SDFFE_NN0P_); - if (patmatch(pattern, "$_SDFF_NN1_")) found_match = true, direct_dict[ID($_SDFF_NN1_)] = ID($_SDFFE_NN1P_); - if (patmatch(pattern, "$_SDFF_NP0_")) found_match = true, direct_dict[ID($_SDFF_NP0_)] = ID($_SDFFE_NP0P_); - if (patmatch(pattern, "$_SDFF_NP1_")) found_match = true, direct_dict[ID($_SDFF_NP1_)] = ID($_SDFFE_NP1P_); - if (patmatch(pattern, "$_SDFF_PN0_")) found_match = true, direct_dict[ID($_SDFF_PN0_)] = ID($_SDFFE_PN0P_); - if (patmatch(pattern, "$_SDFF_PN1_")) found_match = true, direct_dict[ID($_SDFF_PN1_)] = ID($_SDFFE_PN1P_); - if (patmatch(pattern, "$_SDFF_PP0_")) found_match = true, direct_dict[ID($_SDFF_PP0_)] = ID($_SDFFE_PP0P_); - if (patmatch(pattern, "$_SDFF_PP1_")) found_match = true, direct_dict[ID($_SDFF_PP1_)] = ID($_SDFFE_PP1P_); - if (!found_match) - log_cmd_error("No cell types matched pattern '%s'.\n", pattern); - continue; - } - break; - } - extra_args(args, argidx, design); - - if (!direct_dict.empty()) { - log("Selected cell types for direct conversion:\n"); - for (auto &it : direct_dict) - log(" %s -> %s\n", log_id(it.first), log_id(it.second)); - } - - for (auto mod : design->selected_modules()) - if (!mod->has_processes_warn()) - { - if (unmap_mode) { - SigMap sigmap(mod); - for (auto cell : mod->selected_cells()) { - if (cell->type == ID($dffe)) { - if (min_ce_use >= 0) { - int ce_use = 0; - for (auto cell_other : mod->selected_cells()) { - if (cell_other->type != cell->type) - continue; - if (sigmap(cell->getPort(ID::EN)) == sigmap(cell_other->getPort(ID::EN))) - ce_use++; - } - if (ce_use >= min_ce_use) - continue; - } - - RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort(ID::D))); - mod->addDff(NEW_ID, cell->getPort(ID::CLK), tmp, cell->getPort(ID::Q), cell->getParam(ID::CLK_POLARITY).as_bool()); - if (cell->getParam(ID::EN_POLARITY).as_bool()) - mod->addMux(NEW_ID, cell->getPort(ID::Q), cell->getPort(ID::D), cell->getPort(ID::EN), tmp); - else - mod->addMux(NEW_ID, cell->getPort(ID::D), cell->getPort(ID::Q), cell->getPort(ID::EN), tmp); - mod->remove(cell); - continue; - } - if (cell->type.begins_with("$_DFFE_")) { - if (min_ce_use >= 0) { - int ce_use = 0; - for (auto cell_other : mod->selected_cells()) { - if (cell_other->type != cell->type) - continue; - if (sigmap(cell->getPort(ID::E)) == sigmap(cell_other->getPort(ID::E))) - ce_use++; - } - if (ce_use >= min_ce_use) - continue; - } - - bool clk_pol = cell->type.compare(7, 1, "P") == 0; - bool en_pol = cell->type.compare(8, 1, "P") == 0; - RTLIL::SigSpec tmp = mod->addWire(NEW_ID); - mod->addDff(NEW_ID, cell->getPort(ID::C), tmp, cell->getPort(ID::Q), clk_pol); - if (en_pol) - mod->addMux(NEW_ID, cell->getPort(ID::Q), cell->getPort(ID::D), cell->getPort(ID::E), tmp); - else - mod->addMux(NEW_ID, cell->getPort(ID::D), cell->getPort(ID::Q), cell->getPort(ID::E), tmp); - mod->remove(cell); - continue; - } - } - continue; - } - - Dff2dffeWorker worker(mod, direct_dict); - worker.run(); - } - } -} Dff2dffePass; - -PRIVATE_NAMESPACE_END diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc deleted file mode 100644 index 6c2cca4bc..000000000 --- a/passes/techmap/dff2dffs.cc +++ /dev/null @@ -1,165 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * Copyright (C) 2018 David Shah <dave@ds0.me> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct Dff2dffsPass : public Pass { - Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { } - void help() override - { - log("\n"); - log(" dff2dffs [options] [selection]\n"); - log("\n"); - log("Merge synchronous set/reset $_MUX_ cells to create $_SDFF_[NP][NP][01]_, to be run before\n"); - log("dff2dffe for SR over CE priority.\n"); - log("\n"); - log(" -match-init\n"); - log(" Disallow merging synchronous set/reset that has polarity opposite of the\n"); - log(" output wire's init attribute (if any).\n"); - log("\n"); - } - void execute(std::vector<std::string> args, RTLIL::Design *design) override - { - log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n"); - - bool match_init = false; - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - // if (args[argidx] == "-singleton") { - // singleton_mode = true; - // continue; - // } - if (args[argidx] == "-match-init") { - match_init = true; - continue; - } - break; - } - extra_args(args, argidx, design); - - pool<IdString> dff_types; - dff_types.insert(ID($_DFF_N_)); - dff_types.insert(ID($_DFF_P_)); - - for (auto module : design->selected_modules()) - { - log("Merging set/reset $_MUX_ cells into DFFs in %s.\n", log_id(module)); - - SigMap sigmap(module); - dict<SigBit, Cell*> sr_muxes; - vector<Cell*> ff_cells; - - for (auto cell : module->selected_cells()) - { - if (dff_types.count(cell->type)) { - ff_cells.push_back(cell); - continue; - } - - if (cell->type != ID($_MUX_)) - continue; - - SigBit bit_a = sigmap(cell->getPort(ID::A)); - SigBit bit_b = sigmap(cell->getPort(ID::B)); - - if (bit_a.wire == nullptr || bit_b.wire == nullptr) - sr_muxes[sigmap(cell->getPort(ID::Y))] = cell; - } - - for (auto cell : ff_cells) - { - SigSpec sig_d = cell->getPort(ID::D); - - if (GetSize(sig_d) < 1) - continue; - - SigBit bit_d = sigmap(sig_d[0]); - - if (sr_muxes.count(bit_d) == 0) - continue; - - Cell *mux_cell = sr_muxes.at(bit_d); - SigBit bit_a = sigmap(mux_cell->getPort(ID::A)); - SigBit bit_b = sigmap(mux_cell->getPort(ID::B)); - SigBit bit_s = sigmap(mux_cell->getPort(ID::S)); - - SigBit sr_val, sr_sig; - bool invert_sr; - sr_sig = bit_s; - if (bit_a.wire == nullptr) { - bit_d = bit_b; - sr_val = bit_a; - invert_sr = true; - } else { - log_assert(bit_b.wire == nullptr); - bit_d = bit_a; - sr_val = bit_b; - invert_sr = false; - } - - if (match_init) { - SigBit bit_q = cell->getPort(ID::Q); - if (bit_q.wire) { - auto it = bit_q.wire->attributes.find(ID::init); - if (it != bit_q.wire->attributes.end()) { - auto init_val = it->second[bit_q.offset]; - if (init_val == State::S1 && sr_val != State::S1) - continue; - if (init_val == State::S0 && sr_val != State::S0) - continue; - } - } - } - - log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell), - log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type)); - - if (sr_val == State::S1) { - if (cell->type == ID($_DFF_N_)) { - if (invert_sr) cell->type = ID($_SDFF_NN1_); - else cell->type = ID($_SDFF_NP1_); - } else { - log_assert(cell->type == ID($_DFF_P_)); - if (invert_sr) cell->type = ID($_SDFF_PN1_); - else cell->type = ID($_SDFF_PP1_); - } - } else { - if (cell->type == ID($_DFF_N_)) { - if (invert_sr) cell->type = ID($_SDFF_NN0_); - else cell->type = ID($_SDFF_NP0_); - } else { - log_assert(cell->type == ID($_DFF_P_)); - if (invert_sr) cell->type = ID($_SDFF_PN0_); - else cell->type = ID($_SDFF_PP0_); - } - } - cell->setPort(ID::R, sr_sig); - cell->setPort(ID::D, bit_d); - } - } - } -} Dff2dffsPass; - -PRIVATE_NAMESPACE_END diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c22ae8ef0..4a1a74ce9 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -801,11 +801,31 @@ struct TechmapWorker } } + // Handle outputs first, as these cannot be remapped. for (auto &conn : cell->connections()) + { + Wire *twire = tpl->wire(conn.first); + if (!twire->port_output) + continue; + + for (int i = 0; i < GetSize(conn.second); i++) { + RTLIL::SigBit bit = sigmap(conn.second[i]); + RTLIL::SigBit tplbit(twire, i); + cellbits_to_tplbits[bit] = tplbit; + } + } + + // Now handle inputs, remapping as necessary. + for (auto &conn : cell->connections()) + { + Wire *twire = tpl->wire(conn.first); + if (twire->port_output) + continue; + for (int i = 0; i < GetSize(conn.second); i++) { RTLIL::SigBit bit = sigmap(conn.second[i]); - RTLIL::SigBit tplbit(tpl->wire(conn.first), i); + RTLIL::SigBit tplbit(twire, i); if (bit.wire == nullptr) { @@ -820,6 +840,7 @@ struct TechmapWorker else cellbits_to_tplbits[bit] = tplbit; } + } RTLIL::SigSig port_conn; for (auto &it : port_connmap) { @@ -1007,7 +1028,9 @@ struct TechmapPass : public Pass { log("\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("match cells with a type that match the text value of this attribute. Otherwise\n"); - log("the module name will be used to match the cell.\n"); + log("the module name will be used to match the cell. Multiple space-separated cell\n"); + log("types can be listed, and wildcards using [] will be expanded (ie. \"$_DFF_[PN]_\"\n"); + log("is the same as \"$_DFF_P_ $_DFF_N_\").\n"); log("\n"); log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n"); log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n"); @@ -1199,8 +1222,27 @@ struct TechmapPass : public Pass { for (auto module : map->modules()) { if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) { char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str()); - for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) - celltypeMap[RTLIL::escape_id(q)].insert(module->name); + for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) { + std::vector<std::string> queue; + queue.push_back(q); + while (!queue.empty()) { + std::string name = queue.back(); + queue.pop_back(); + auto pos = name.find('['); + if (pos == std::string::npos) { + // No further expansion. + celltypeMap[RTLIL::escape_id(name)].insert(module->name); + } else { + // Expand [] in this name. + auto epos = name.find(']', pos); + if (epos == std::string::npos) + log_error("Malformed techmap_celltype pattern %s\n", q); + for (size_t i = pos + 1; i < epos; i++) { + queue.push_back(name.substr(0, pos) + name[i] + name.substr(epos + 1, std::string::npos)); + } + } + } + } free(p); } else { IdString module_name = module->name.begins_with("\\$") ? @@ -1208,8 +1250,15 @@ struct TechmapPass : public Pass { celltypeMap[module_name].insert(module->name); } } - for (auto &i : celltypeMap) + log_debug("Cell type mappings to use:\n"); + for (auto &i : celltypeMap) { i.second.sort(RTLIL::sort_by_id_str()); + std::string maps = ""; + for (auto &map : i.second) + maps += stringf(" %s", log_id(map)); + log_debug(" %s:%s\n", log_id(i.first), maps.c_str()); + } + log_debug("\n"); for (auto module : design->modules()) worker.module_queue.insert(module); |