diff options
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/deminout.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/extract_reduce.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/flowmap.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/iopadmap.cc | 16 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 4 |
5 files changed, 20 insertions, 6 deletions
diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index 35d43b106..a7dce9c81 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -113,7 +113,7 @@ struct DeminoutPass : public Pass { { if (bits_numports[bit] > 1 || bits_inout.count(bit)) new_input = true, new_output = true; - if (bit == State::S0 || bit == State::S1) + if (!bit.wire) new_output = true; if (bits_written.count(bit)) { new_output = true; diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 11cfddcd9..92c52398c 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -286,7 +286,7 @@ struct ExtractReducePass : public Pass SigSpec input; for (auto b : input_pool) if (input_pool_intermed.count(b) == 0) - input.append_bit(b); + input.append(b); SigBit output = sigmap(head_cell->getPort(ID::Y)[0]); diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index a2ad87f7d..427b72a6a 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1405,7 +1405,7 @@ struct FlowmapWorker RTLIL::SigSpec lut_a, lut_y = node; for (auto input_node : input_nodes) - lut_a.append_bit(input_node); + lut_a.append(input_node); lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table); diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 8b1862237..f754aecb8 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -229,11 +229,13 @@ struct IopadmapPass : public Pass { for (auto module : design->selected_modules()) { dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits; + pool<SigSig> remove_conns; if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty()) { dict<SigBit, Cell *> tbuf_bits; pool<SigBit> driven_bits; + dict<SigBit, SigSig> z_conns; // Gather tristate buffers and always-on drivers. for (auto cell : module->cells()) @@ -252,8 +254,10 @@ struct IopadmapPass : public Pass { for (int i = 0; i < GetSize(conn.first); i++) { SigBit dstbit = conn.first[i]; SigBit srcbit = conn.second[i]; - if (!srcbit.wire && srcbit.data == State::Sz) + if (!srcbit.wire && srcbit.data == State::Sz) { + z_conns[dstbit] = conn; continue; + } driven_bits.insert(dstbit); } @@ -302,6 +306,8 @@ struct IopadmapPass : public Pass { // enable. en_sig = SigBit(State::S0); data_sig = SigBit(State::Sx); + if (z_conns.count(wire_bit)) + remove_conns.insert(z_conns[wire_bit]); } if (wire->port_input) @@ -454,6 +460,14 @@ struct IopadmapPass : public Pass { } } + if (!remove_conns.empty()) { + std::vector<SigSig> new_conns; + for (auto &conn : module->connections()) + if (!remove_conns.count(conn)) + new_conns.push_back(conn); + module->new_connections(new_conns); + } + for (auto &it : rewrite_bits) { RTLIL::Wire *wire = it.first; RTLIL::Wire *new_wire = module->addWire( diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 10001baaa..0a67d9dbe 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -906,8 +906,8 @@ struct TechmapWorker RTLIL::SigSig port_conn; for (auto &it : port_connmap) { - port_conn.first.append_bit(it.first); - port_conn.second.append_bit(it.second); + port_conn.first.append(it.first); + port_conn.second.append(it.second); } tpl->connect(port_conn); |