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-rw-r--r--passes/techmap/dfflibmap.cc4
-rw-r--r--passes/techmap/extract.cc30
-rw-r--r--passes/techmap/simplemap.cc6
-rw-r--r--passes/techmap/techmap.cc36
4 files changed, 38 insertions, 38 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 7712d18b9..16518b7df 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -29,7 +29,7 @@ struct cell_mapping {
std::string cell_name;
std::map<std::string, char> ports;
};
-static std::map<std::string, cell_mapping> cell_mappings;
+static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
static void logmap(std::string dff)
{
@@ -319,7 +319,7 @@ static bool expand_cellmap(std::string pattern, std::string inv)
bool return_status = false;
for (auto &it : cell_mappings) {
- std::string from = it.first, to = it.first;
+ std::string from = it.first.str(), to = it.first.str();
if (from.size() != pattern.size())
continue;
for (size_t i = 0; i < from.size(); i++) {
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 53bc00daf..6ebac265c 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -34,7 +34,7 @@ namespace
{
public:
bool ignore_parameters;
- std::set<std::pair<std::string, std::string>> ignored_parameters;
+ std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> ignored_parameters;
std::set<RTLIL::IdString> cell_attr, wire_attr;
SubCircuitSolver() : ignore_parameters(false)
@@ -106,10 +106,10 @@ namespace
if (!ignore_parameters) {
std::map<RTLIL::IdString, RTLIL::Const> needle_param, haystack_param;
for (auto &it : needleCell->parameters)
- if (!ignored_parameters.count(std::pair<std::string, std::string>(needleCell->type, it.first)))
+ if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(needleCell->type, it.first)))
needle_param[it.first] = unified_param(needleCell->type, it.first, it.second);
for (auto &it : haystackCell->parameters)
- if (!ignored_parameters.count(std::pair<std::string, std::string>(haystackCell->type, it.first)))
+ if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(haystackCell->type, it.first)))
haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second);
if (needle_param != haystack_param)
return false;
@@ -127,7 +127,7 @@ namespace
for (auto &conn : needleCell->connections())
{
RTLIL::SigSpec needleSig = conn.second;
- RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first));
+ RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
@@ -201,14 +201,14 @@ namespace
if (sel && !sel->selected(mod, cell))
continue;
- std::string type = cell->type;
+ std::string type = cell->type.str();
if (sel == NULL && type.substr(0, 2) == "\\$")
type = type.substr(1);
- graph.createNode(cell->name, type, (void*)cell);
+ graph.createNode(cell->name.str(), type, (void*)cell);
for (auto &conn : cell->connections())
{
- graph.createPort(cell->name, conn.first, conn.second.size());
+ graph.createPort(cell->name.str(), conn.first.str(), conn.second.size());
if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0)
continue;
@@ -226,9 +226,9 @@ namespace
if (bit == RTLIL::State::S0) node = "$const$0";
if (bit == RTLIL::State::S1) node = "$const$1";
if (bit == RTLIL::State::Sz) node = "$const$z";
- graph.createConnection(cell->name, conn.first, i, node, "\\Y", 0);
+ graph.createConnection(cell->name.str(), conn.first.str(), i, node, "\\Y", 0);
} else
- graph.createConstant(cell->name, conn.first, i, int(bit.data));
+ graph.createConstant(cell->name.str(), conn.first.str(), i, int(bit.data));
continue;
}
@@ -246,7 +246,7 @@ namespace
}
bit_ref_t &bit_ref = sig_bit_ref[bit];
- graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name, conn.first, i);
+ graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), conn.first.str(), i);
}
}
}
@@ -293,7 +293,7 @@ namespace
RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
{
SigMap sigmap(needle);
- SigSet<std::pair<std::string, int>> sig2port;
+ SigSet<std::pair<RTLIL::IdString, int>> sig2port;
// create new cell
RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
@@ -303,7 +303,7 @@ namespace
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
for (int i = 0; i < wire->width; i++)
- sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
+ sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<RTLIL::IdString, int>(wire->name, i));
cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
}
}
@@ -320,10 +320,10 @@ namespace
for (auto &conn : needle_cell->connections()) {
RTLIL::SigSpec sig = sigmap(conn.second);
- if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
+ if (mapping.portMapping.count(conn.first.str()) > 0 && sig2port.has(sigmap(sig))) {
for (int i = 0; i < sig.size(); i++)
for (auto &port : sig2port.find(sig[i])) {
- RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first]).extract(i, 1);
+ RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first.str()]).extract(i, 1);
RTLIL::SigSpec new_sig = cell->getPort(port.first);
new_sig.replace(port.second, bitsig);
cell->setPort(port.first, new_sig);
@@ -561,7 +561,7 @@ struct ExtractPass : public Pass {
continue;
}
if (args[argidx] == "-ignore_param" && argidx+2 < args.size()) {
- solver.ignored_parameters.insert(std::pair<std::string, std::string>(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2])));
+ solver.ignored_parameters.insert(std::pair<RTLIL::IdString, RTLIL::IdString>(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2])));
argidx += 2;
continue;
}
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index f1f334f6e..960578b06 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -24,7 +24,7 @@
#include <stdio.h>
#include <string.h>
-extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
+extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{
@@ -382,7 +382,7 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
-void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
+void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
{
mappers["$not"] = simplemap_not;
mappers["$pos"] = simplemap_pos;
@@ -431,7 +431,7 @@ struct SimplemapPass : public Pass {
log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
extra_args(args, 1, design);
- std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
+ std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
simplemap_get_mappers(mappers);
for (auto mod : design->modules()) {
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 1f812e52f..2bcd3003e 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -29,7 +29,7 @@
#include "passes/techmap/techmap.inc"
// see simplemap.cc
-extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
+extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
static void apply_prefix(std::string prefix, std::string &id)
{
@@ -44,7 +44,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
std::vector<RTLIL::SigChunk> chunks = sig;
for (auto &chunk : chunks)
if (chunk.wire != NULL) {
- std::string wire_name = chunk.wire->name;
+ std::string wire_name = chunk.wire->name.str();
apply_prefix(prefix, wire_name);
log_assert(module->wires_.count(wire_name) > 0);
chunk.wire = module->wires_[wire_name];
@@ -54,7 +54,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
struct TechmapWorker
{
- std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
+ std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
std::map<RTLIL::Module*, bool> techmap_do_cache;
std::set<RTLIL::Module*> module_queue;
@@ -80,7 +80,7 @@ struct TechmapWorker
std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
{
std::string constmap_info;
- std::map<RTLIL::SigBit, std::pair<std::string, int>> connbits_map;
+ std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
for (auto conn : cell->connections())
for (int i = 0; i < SIZE(conn.second); i++) {
@@ -96,7 +96,7 @@ struct TechmapWorker
constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
} else
- connbits_map[bit] = std::pair<std::string, int>(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data);
+ connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data);
}
return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
@@ -156,7 +156,7 @@ struct TechmapWorker
for (auto &it : tpl->cells_)
if (it.first == "\\_TECHMAP_REPLACE_") {
orig_cell_name = cell->name;
- module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name);
+ module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break;
}
@@ -165,8 +165,8 @@ struct TechmapWorker
for (auto &it : tpl->wires_) {
if (it.second->port_id > 0)
positional_ports[stringf("$%d", it.second->port_id)] = it.first;
- std::string w_name = it.second->name;
- apply_prefix(cell->name, w_name);
+ std::string w_name = it.second->name.str();
+ apply_prefix(cell->name.str(), w_name);
RTLIL::Wire *w = module->addWire(w_name, it.second);
w->port_input = false;
w->port_output = false;
@@ -192,11 +192,11 @@ struct TechmapWorker
if (w->port_output) {
c.first = it.second;
c.second = RTLIL::SigSpec(w);
- apply_prefix(cell->name, c.second, module);
+ apply_prefix(cell->name.str(), c.second, module);
} else {
c.first = RTLIL::SigSpec(w);
c.second = it.second;
- apply_prefix(cell->name, c.first, module);
+ apply_prefix(cell->name.str(), c.first, module);
}
if (c.second.size() > c.first.size())
c.second.remove(c.first.size(), c.second.size() - c.first.size());
@@ -219,12 +219,12 @@ struct TechmapWorker
for (auto &it : tpl->cells_)
{
- RTLIL::IdString c_name = it.second->name;
+ std::string c_name = it.second->name.str();
if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
c_name = orig_cell_name;
else
- apply_prefix(cell->name, c_name);
+ apply_prefix(cell->name.str(), c_name);
RTLIL::Cell *c = module->addCell(c_name, it.second);
design->select(module, c);
@@ -233,15 +233,15 @@ struct TechmapWorker
c->type = c->type.substr(1);
for (auto &it2 : c->connections_) {
- apply_prefix(cell->name, it2.second, module);
+ apply_prefix(cell->name.str(), it2.second, module);
port_signal_map.apply(it2.second);
}
}
for (auto &it : tpl->connections()) {
RTLIL::SigSig c = it;
- apply_prefix(cell->name, c.first, module);
- apply_prefix(cell->name, c.second, module);
+ apply_prefix(cell->name.str(), c.first, module);
+ apply_prefix(cell->name.str(), c.second, module);
port_signal_map.apply(c.first);
port_signal_map.apply(c.second);
module->connect(c);
@@ -271,7 +271,7 @@ struct TechmapWorker
continue;
if (celltypeMap.count(cell->type) == 0) {
- if (assert_mode && cell->type.back() != '_')
+ if (assert_mode && cell->type.str().back() != '_')
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type));
continue;
}
@@ -313,7 +313,7 @@ struct TechmapWorker
for (auto &tpl_name : celltypeMap.at(cell->type))
{
- std::string derived_name = tpl_name;
+ RTLIL::IdString derived_name = tpl_name;
RTLIL::Module *tpl = map->modules_[tpl_name];
std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
@@ -499,7 +499,7 @@ struct TechmapWorker
if (!wire->port_input || wire->port_output)
continue;
- std::string port_name = wire->name;
+ RTLIL::IdString port_name = wire->name;
tpl->rename(wire, NEW_ID);
RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 21:34:00 +0000