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-rw-r--r--passes/techmap/abc.cc29
-rw-r--r--passes/techmap/dffinit.cc3
-rw-r--r--passes/techmap/flowmap.cc4
-rw-r--r--passes/techmap/libparse.cc2
-rw-r--r--passes/techmap/muxcover.cc196
-rw-r--r--passes/techmap/shregmap.cc35
-rw-r--r--passes/techmap/zinit.cc2
7 files changed, 198 insertions, 73 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 547115459..5b19d84fb 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -330,20 +330,33 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr)
{
std::string abc_sname = abc_name.substr(1);
- if (abc_sname.substr(0, 5) == "ys__n") {
- bool inv = abc_sname.back() == 'v';
- if (inv) abc_sname.pop_back();
+ bool isnew = false;
+ if (abc_sname.substr(0, 4) == "new_")
+ {
+ abc_sname.erase(0, 4);
+ isnew = true;
+ }
+ if (abc_sname.substr(0, 5) == "ys__n")
+ {
abc_sname.erase(0, 5);
- if (abc_sname.find_last_not_of("012345689") == std::string::npos) {
+ if (std::isdigit(abc_sname.at(0)))
+ {
int sid = std::stoi(abc_sname);
- for (auto sig : signal_list) {
- if (sig.id == sid && sig.bit.wire != nullptr) {
+ size_t postfix_start = abc_sname.find_first_not_of("0123456789");
+ std::string postfix = postfix_start != std::string::npos ? abc_sname.substr(postfix_start) : "";
+
+ if (sid < GetSize(signal_list))
+ {
+ auto sig = signal_list.at(sid);
+ if (sig.bit.wire != nullptr)
+ {
std::stringstream sstr;
sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1);
if (sig.bit.wire->width != 1)
sstr << "[" << sig.bit.offset << "]";
- if (inv)
- sstr << "_inv";
+ if (isnew)
+ sstr << "_new";
+ sstr << postfix;
if (orig_wire != nullptr)
*orig_wire = sig.bit.wire;
return sstr.str();
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 48390488e..0ad33dc0e 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -102,7 +102,8 @@ struct DffinitPass : public Pass {
if (wire->attributes.count("\\init")) {
Const value = wire->attributes.at("\\init");
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
- init_bits[sigmap(SigBit(wire, i))] = value[i];
+ if (value[i] != State::Sx)
+ init_bits[sigmap(SigBit(wire, i))] = value[i];
}
if (wire->port_output)
for (auto bit : sigmap(wire))
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index 0b7931e48..f5892a60e 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -397,7 +397,6 @@ struct FlowGraph
pool<RTLIL::SigBit> x, xi;
NodePrime source_prime = {source, true};
- NodePrime sink_prime = {sink, false};
pool<NodePrime> visited;
vector<NodePrime> worklist = {source_prime};
while (!worklist.empty())
@@ -1382,7 +1381,8 @@ struct FlowmapWorker
vector<RTLIL::SigBit> input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end());
RTLIL::Const lut_table(State::Sx, max(1 << input_nodes.size(), 1 << minlut));
- for (unsigned i = 0; i < (1 << input_nodes.size()); i++)
+ unsigned const mask = 1 << input_nodes.size();
+ for (unsigned i = 0; i < mask; i++)
{
ce.push();
for (size_t n = 0; n < input_nodes.size(); n++)
diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index 991cc4498..349ccc115 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -94,7 +94,7 @@ int LibertyParser::lexer(std::string &str)
// search for identifiers, numbers, plus or minus.
if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') {
- str = c;
+ str = static_cast<char>(c);
while (1) {
c = f.get();
if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.')
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index 12da9ed0c..b0722134e 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -23,6 +23,7 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
+#define COST_DMUX 90
#define COST_MUX2 100
#define COST_MUX4 220
#define COST_MUX8 460
@@ -57,6 +58,13 @@ struct MuxcoverWorker
bool use_mux8;
bool use_mux16;
bool nodecode;
+ bool nopartial;
+
+ int cost_dmux;
+ int cost_mux2;
+ int cost_mux4;
+ int cost_mux8;
+ int cost_mux16;
MuxcoverWorker(Module *module) : module(module), sigmap(module)
{
@@ -64,6 +72,12 @@ struct MuxcoverWorker
use_mux8 = false;
use_mux16 = false;
nodecode = false;
+ nopartial = false;
+ cost_dmux = COST_DMUX;
+ cost_mux2 = COST_MUX2;
+ cost_mux4 = COST_MUX4;
+ cost_mux8 = COST_MUX8;
+ cost_mux16 = COST_MUX16;
decode_mux_counter = 0;
}
@@ -124,13 +138,20 @@ struct MuxcoverWorker
log(" Finished treeification: Found %d trees.\n", GetSize(tree_list));
}
- bool follow_muxtree(SigBit &ret_bit, tree_t &tree, SigBit bit, const char *path)
+ bool follow_muxtree(SigBit &ret_bit, tree_t &tree, SigBit bit, const char *path, bool first_layer = true)
{
if (*path) {
- if (tree.muxes.count(bit) == 0)
- return false;
+ if (tree.muxes.count(bit) == 0) {
+ if (first_layer || nopartial)
+ return false;
+ if (path[0] == 'S')
+ ret_bit = State::Sx;
+ else
+ ret_bit = bit;
+ return true;
+ }
char port_name[3] = {'\\', *path, 0};
- return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(port_name)), path+1);
+ return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(port_name)), path+1, false);
} else {
ret_bit = bit;
return true;
@@ -139,7 +160,7 @@ struct MuxcoverWorker
int prepare_decode_mux(SigBit &A, SigBit B, SigBit sel, SigBit bit)
{
- if (A == B)
+ if (A == B || sel == State::Sx)
return 0;
tuple<SigBit, SigBit, SigBit> key(A, B, sel);
@@ -157,7 +178,10 @@ struct MuxcoverWorker
if (std::get<2>(entry))
return 0;
- return COST_MUX2 / GetSize(std::get<1>(entry));
+ if (A == State::Sx || B == State::Sx)
+ return 0;
+
+ return cost_dmux / GetSize(std::get<1>(entry));
}
void implement_decode_mux(SigBit ctrl_bit)
@@ -174,9 +198,32 @@ struct MuxcoverWorker
implement_decode_mux(std::get<0>(key));
implement_decode_mux(std::get<1>(key));
- module->addMuxGate(NEW_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit);
+ if (std::get<0>(key) == State::Sx) {
+ module->addBufGate(NEW_ID, std::get<1>(key), ctrl_bit);
+ } else if (std::get<1>(key) == State::Sx) {
+ module->addBufGate(NEW_ID, std::get<0>(key), ctrl_bit);
+ } else {
+ module->addMuxGate(NEW_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit);
+ decode_mux_counter++;
+ }
std::get<2>(entry) = true;
- decode_mux_counter++;
+ }
+
+ void find_best_covers(tree_t &tree, const vector<SigBit> &bits)
+ {
+ for (auto bit : bits)
+ find_best_cover(tree, bit);
+ }
+
+ int sum_best_covers(tree_t &tree, const vector<SigBit> &bits)
+ {
+ int sum = 0;
+ for (auto bit : pool<SigBit>(bits.begin(), bits.end())) {
+ int cost = tree.newmuxes.at(bit).cost;
+ log_debug(" Best cost for %s: %d\n", log_signal(bit), cost);
+ sum += cost;
+ }
+ return sum;
}
int find_best_cover(tree_t &tree, SigBit bit)
@@ -209,9 +256,13 @@ struct MuxcoverWorker
mux.inputs.push_back(B);
mux.selects.push_back(S1);
- mux.cost += COST_MUX2;
- mux.cost += find_best_cover(tree, A);
- mux.cost += find_best_cover(tree, B);
+ find_best_covers(tree, mux.inputs);
+ log_debug(" Decode cost for mux2 at %s: %d\n", log_signal(bit), mux.cost);
+
+ mux.cost += cost_mux2;
+ mux.cost += sum_best_covers(tree, mux.inputs);
+
+ log_debug(" Cost of mux2 at %s: %d\n", log_signal(bit), mux.cost);
best_mux = mux;
}
@@ -247,13 +298,15 @@ struct MuxcoverWorker
mux.selects.push_back(S1);
mux.selects.push_back(T1);
- mux.cost += COST_MUX4;
- mux.cost += find_best_cover(tree, A);
- mux.cost += find_best_cover(tree, B);
- mux.cost += find_best_cover(tree, C);
- mux.cost += find_best_cover(tree, D);
+ find_best_covers(tree, mux.inputs);
+ log_debug(" Decode cost for mux4 at %s: %d\n", log_signal(bit), mux.cost);
+
+ mux.cost += cost_mux4;
+ mux.cost += sum_best_covers(tree, mux.inputs);
+
+ log_debug(" Cost of mux4 at %s: %d\n", log_signal(bit), mux.cost);
- if (best_mux.cost > mux.cost)
+ if (best_mux.cost >= mux.cost)
best_mux = mux;
}
}
@@ -310,17 +363,15 @@ struct MuxcoverWorker
mux.selects.push_back(T1);
mux.selects.push_back(U1);
- mux.cost += COST_MUX8;
- mux.cost += find_best_cover(tree, A);
- mux.cost += find_best_cover(tree, B);
- mux.cost += find_best_cover(tree, C);
- mux.cost += find_best_cover(tree, D);
- mux.cost += find_best_cover(tree, E);
- mux.cost += find_best_cover(tree, F);
- mux.cost += find_best_cover(tree, G);
- mux.cost += find_best_cover(tree, H);
-
- if (best_mux.cost > mux.cost)
+ find_best_covers(tree, mux.inputs);
+ log_debug(" Decode cost for mux8 at %s: %d\n", log_signal(bit), mux.cost);
+
+ mux.cost += cost_mux8;
+ mux.cost += sum_best_covers(tree, mux.inputs);
+
+ log_debug(" Cost of mux8 at %s: %d\n", log_signal(bit), mux.cost);
+
+ if (best_mux.cost >= mux.cost)
best_mux = mux;
}
}
@@ -414,25 +465,15 @@ struct MuxcoverWorker
mux.selects.push_back(U1);
mux.selects.push_back(V1);
- mux.cost += COST_MUX16;
- mux.cost += find_best_cover(tree, A);
- mux.cost += find_best_cover(tree, B);
- mux.cost += find_best_cover(tree, C);
- mux.cost += find_best_cover(tree, D);
- mux.cost += find_best_cover(tree, E);
- mux.cost += find_best_cover(tree, F);
- mux.cost += find_best_cover(tree, G);
- mux.cost += find_best_cover(tree, H);
- mux.cost += find_best_cover(tree, I);
- mux.cost += find_best_cover(tree, J);
- mux.cost += find_best_cover(tree, K);
- mux.cost += find_best_cover(tree, L);
- mux.cost += find_best_cover(tree, M);
- mux.cost += find_best_cover(tree, N);
- mux.cost += find_best_cover(tree, O);
- mux.cost += find_best_cover(tree, P);
-
- if (best_mux.cost > mux.cost)
+ find_best_covers(tree, mux.inputs);
+ log_debug(" Decode cost for mux16 at %s: %d\n", log_signal(bit), mux.cost);
+
+ mux.cost += cost_mux16;
+ mux.cost += sum_best_covers(tree, mux.inputs);
+
+ log_debug(" Cost of mux16 at %s: %d\n", log_signal(bit), mux.cost);
+
+ if (best_mux.cost >= mux.cost)
best_mux = mux;
}
}
@@ -528,6 +569,7 @@ struct MuxcoverWorker
void treecover(tree_t &tree)
{
int count_muxes_by_type[4] = {0, 0, 0, 0};
+ log_debug(" Searching for best cover for tree at %s.\n", log_signal(tree.root));
find_best_cover(tree, tree.root);
implement_best_cover(tree, tree.root, count_muxes_by_type);
log(" Replaced tree at %s: %d MUX2, %d MUX4, %d MUX8, %d MUX16\n", log_signal(tree.root),
@@ -544,12 +586,13 @@ struct MuxcoverWorker
log(" Covering trees:\n");
- // pre-fill cache of decoder muxes
- if (!nodecode)
+ if (!nodecode) {
+ log_debug(" Populating cache of decoder muxes.\n");
for (auto &tree : tree_list) {
find_best_cover(tree, tree.root);
tree.newmuxes.clear();
}
+ }
for (auto &tree : tree_list)
treecover(tree);
@@ -569,15 +612,25 @@ struct MuxcoverPass : public Pass {
log("\n");
log("Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells\n");
log("\n");
- log(" -mux4, -mux8, -mux16\n");
- log(" Use the specified types of MUXes. If none of those options are used,\n");
- log(" the effect is the same as if all of them where used.\n");
+ log(" -mux4[=cost], -mux8[=cost], -mux16[=cost]\n");
+ log(" Use the specified types of MUXes (with optional integer costs). If none\n");
+ log(" of these options are given, the effect is the same as if all of them are.\n");
+ log(" Default costs: $_MUX_ = %d, $_MUX4_ = %d,\n", COST_MUX2, COST_MUX4);
+ log(" $_MUX8_ = %d, $_MUX16_ = %d\n", COST_MUX8, COST_MUX16);
+ log("\n");
+ log(" -dmux=cost\n");
+ log(" Use the specified cost for $_MUX_ cells used in decoders.\n");
+ log(" Default cost: %d\n", COST_DMUX);
log("\n");
log(" -nodecode\n");
log(" Do not insert decoder logic. This reduces the number of possible\n");
log(" substitutions, but guarantees that the resulting circuit is not\n");
log(" less efficient than the original circuit.\n");
log("\n");
+ log(" -nopartial\n");
+ log(" Do not consider mappings that use $_MUX<N>_ to select from less\n");
+ log(" than <N> different signals.\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
@@ -587,26 +640,52 @@ struct MuxcoverPass : public Pass {
bool use_mux8 = false;
bool use_mux16 = false;
bool nodecode = false;
+ bool nopartial = false;
+ int cost_dmux = COST_DMUX;
+ int cost_mux4 = COST_MUX4;
+ int cost_mux8 = COST_MUX8;
+ int cost_mux16 = COST_MUX16;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
- if (args[argidx] == "-mux4") {
+ const auto &arg = args[argidx];
+ if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") {
use_mux4 = true;
+ if (arg.size() > 5) {
+ if (arg[5] != '=') break;
+ cost_mux4 = atoi(arg.substr(6).c_str());
+ }
continue;
}
- if (args[argidx] == "-mux8") {
+ if (arg.size() >= 5 && arg.substr(0,5) == "-mux8") {
use_mux8 = true;
+ if (arg.size() > 5) {
+ if (arg[5] != '=') break;
+ cost_mux8 = atoi(arg.substr(6).c_str());
+ }
continue;
}
- if (args[argidx] == "-mux16") {
+ if (arg.size() >= 6 && arg.substr(0,6) == "-mux16") {
use_mux16 = true;
+ if (arg.size() > 6) {
+ if (arg[6] != '=') break;
+ cost_mux16 = atoi(arg.substr(7).c_str());
+ }
continue;
}
- if (args[argidx] == "-nodecode") {
+ if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") {
+ cost_dmux = atoi(arg.substr(6).c_str());
+ continue;
+ }
+ if (arg == "-nodecode") {
nodecode = true;
continue;
}
+ if (arg == "-nopartial") {
+ nopartial = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -623,7 +702,12 @@ struct MuxcoverPass : public Pass {
worker.use_mux4 = use_mux4;
worker.use_mux8 = use_mux8;
worker.use_mux16 = use_mux16;
+ worker.cost_dmux = cost_dmux;
+ worker.cost_mux4 = cost_mux4;
+ worker.cost_mux8 = cost_mux8;
+ worker.cost_mux16 = cost_mux16;
worker.nodecode = nodecode;
+ worker.nopartial = nopartial;
worker.run();
}
}
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index a541b33be..004ab1eb9 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -178,7 +178,17 @@ struct ShregmapTechXilinx7 : ShregmapTech
// Only map if $shiftx exclusively covers the shift register
if (shiftx->type == "$shiftx") {
- if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
+ if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int())
+ return false;
+ // Due to padding the most significant bits of A may be 1'bx,
+ // and if so, discount them
+ if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) {
+ const SigSpec A = shiftx->getPort("\\A");
+ const int A_width = shiftx->getParam("\\A_WIDTH").as_int();
+ for (int i = GetSize(taps); i < A_width; ++i)
+ if (A[i] != RTLIL::Sx) return false;
+ }
+ else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
return false;
}
else if (shiftx->type == "$mux") {
@@ -283,10 +293,22 @@ struct ShregmapWorker
if (opts.init || sigbit_init.count(q_bit) == 0)
{
- if (sigbit_chain_next.count(d_bit)) {
+ auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
+ if (!r.second) {
+ // Insertion not successful means that d_bit is already
+ // connected to another register, thus mark it as a
+ // non chain user ...
sigbit_with_non_chain_users.insert(d_bit);
- } else
- sigbit_chain_next[d_bit] = cell;
+ // ... and clone d_bit into another wire, and use that
+ // wire as a different key in the d_bit-to-cell dictionary
+ // so that it can be identified as another chain
+ // (omitting this common flop)
+ // Link: https://github.com/YosysHQ/yosys/pull/1085
+ Wire *wire = module->addWire(NEW_ID);
+ module->connect(wire, d_bit);
+ sigmap.add(wire, d_bit);
+ sigbit_chain_next.insert(std::make_pair(wire, cell));
+ }
sigbit_chain_prev[q_bit] = cell;
continue;
@@ -595,6 +617,11 @@ struct ShregmapPass : public Pass {
log("\n");
log(" -tech greenpak4\n");
log(" map to greenpak4 shift registers.\n");
+ log(" this option also implies -clkpol pos -zinit\n");
+ log("\n");
+ log(" -tech xilinx\n");
+ log(" map to xilinx dynamic-length shift registers.\n");
+ log(" this option also implies -params -init\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc
index b46147fb9..2aefc091d 100644
--- a/passes/techmap/zinit.cc
+++ b/passes/techmap/zinit.cc
@@ -46,7 +46,7 @@ struct ZinitPass : public Pass {
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
- if (args[argidx] == "-singleton") {
+ if (args[argidx] == "-all") {
all_mode = true;
continue;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-30 04:30:04 +0000