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-rw-r--r--passes/techmap/abc.cc86
-rw-r--r--passes/techmap/abc9.cc26
-rw-r--r--passes/techmap/alumacc.cc34
-rw-r--r--passes/techmap/deminout.cc4
-rw-r--r--passes/techmap/dff2dffe.cc18
-rw-r--r--passes/techmap/dff2dffs.cc10
-rw-r--r--passes/techmap/dfflibmap.cc6
-rw-r--r--passes/techmap/extract_counter.cc38
-rw-r--r--passes/techmap/extract_fa.cc22
-rw-r--r--passes/techmap/extract_reduce.cc20
-rw-r--r--passes/techmap/iopadmap.cc4
-rw-r--r--passes/techmap/lut2mux.cc4
-rw-r--r--passes/techmap/maccmap.cc28
-rw-r--r--passes/techmap/muxcover.cc30
-rw-r--r--passes/techmap/nlutmap.cc2
-rw-r--r--passes/techmap/pmuxtree.cc8
-rw-r--r--passes/techmap/shregmap.cc22
-rw-r--r--passes/techmap/simplemap.cc120
-rw-r--r--passes/techmap/techmap.cc2
-rw-r--r--passes/techmap/tribuf.cc22
20 files changed, 253 insertions, 253 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 20ebc73c8..205f05ab9 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -211,8 +211,8 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_y);
@@ -225,9 +225,9 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_b = cell->getPort(ID(B));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_b = cell->getPort(ID::B);
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@@ -261,10 +261,10 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_b = cell->getPort(ID(B));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID(S));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@@ -283,10 +283,10 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_b = cell->getPort(ID(B));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_c = cell->getPort(ID(C));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@@ -305,11 +305,11 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_b = cell->getPort(ID(B));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_c = cell->getPort(ID(C));
RTLIL::SigSpec sig_d = cell->getPort(ID(D));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@@ -1042,63 +1042,63 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type.in(ID(ZERO), ID(ONE))) {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]);
+ conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]);
conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1);
module->connect(conn);
continue;
}
if (c->type == ID(BUF)) {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]);
- conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]);
+ conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]);
+ conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]);
module->connect(conn);
continue;
}
if (c->type == ID(NOT)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
- cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
- cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
+ cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
+ cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
- cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
- cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
- cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
+ cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
+ cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
+ cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type.in(ID(MUX), ID(NMUX))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
- cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
- cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
+ cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
+ cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
- cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
+ cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == ID(MUX4)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
- cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
- cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
+ cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
+ cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
- cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
+ cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == ID(MUX8)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
- cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
- cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
+ cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
+ cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)]));
@@ -1108,15 +1108,15 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)]));
- cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
+ cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == ID(MUX16)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
- cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
- cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
+ cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
+ cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)]));
@@ -1135,28 +1135,28 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)]));
cell->setPort(ID(V), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(V)).as_wire()->name)]));
- cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
+ cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI3), ID(OAI3))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
- cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
- cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
+ cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
+ cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
- cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
+ cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI4), ID(OAI4))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
- cell->setPort(ID(A), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)]));
- cell->setPort(ID(B), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(B)).as_wire()->name)]));
+ cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
+ cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
- cell->setPort(ID(Y), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)]));
+ cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
@@ -1207,9 +1207,9 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
continue;
}
- if (c->type == ID($lut) && GetSize(c->getPort(ID(A))) == 1 && c->getParam(ID(LUT)).as_int() == 2) {
- SigSpec my_a = module->wires_[remap_name(c->getPort(ID(A)).as_wire()->name)];
- SigSpec my_y = module->wires_[remap_name(c->getPort(ID(Y)).as_wire()->name)];
+ if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)).as_int() == 2) {
+ SigSpec my_a = module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)];
+ SigSpec my_y = module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)];
module->connect(my_y, my_a);
continue;
}
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 752535f34..b3de7cdc5 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -582,13 +582,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Cell *cell = nullptr;
if (c->type == ID($_NOT_)) {
- RTLIL::SigBit a_bit = c->getPort(ID(A));
- RTLIL::SigBit y_bit = c->getPort(ID(Y));
+ RTLIL::SigBit a_bit = c->getPort(ID::A);
+ RTLIL::SigBit y_bit = c->getPort(ID::Y);
bit_users[a_bit].insert(c->name);
bit_drivers[y_bit].insert(c->name);
if (!a_bit.wire) {
- c->setPort(ID(Y), module->addWire(NEW_ID));
+ c->setPort(ID::Y, module->addWire(NEW_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@@ -616,7 +616,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
- bit2sinks[cell->getPort(ID(A))].push_back(cell);
+ bit2sinks[cell->getPort(ID::A)].push_back(cell);
cell_stats[ID($lut)]++;
}
else
@@ -632,9 +632,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Cell *existing_cell = nullptr;
if (c->type == ID($lut)) {
- if (GetSize(c->getPort(ID(A))) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
- SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID(A)).as_wire()->name));
- SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID(Y)).as_wire()->name));
+ if (GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
+ SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID::A).as_wire()->name));
+ SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID::Y).as_wire()->name));
module->connect(my_y, my_a);
if (markgroups) c->attributes[ID(abcgroup)] = map_autoidx;
log_abort();
@@ -751,8 +751,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
if (it == not2drivers.end())
continue;
RTLIL::Cell *driver_lut = it->second;
- RTLIL::SigBit a_bit = not_cell->getPort(ID(A));
- RTLIL::SigBit y_bit = not_cell->getPort(ID(Y));
+ RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
+ RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
RTLIL::Const driver_mask;
a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
@@ -768,7 +768,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// Push downstream LUTs past inverter
for (auto sink_cell : jt->second) {
- SigSpec A = sink_cell->getPort(ID(A));
+ SigSpec A = sink_cell->getPort(ID::A);
RTLIL::Const mask = sink_cell->getParam(ID(LUT));
int index = 0;
for (; index < GetSize(A); index++)
@@ -782,7 +782,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
i += 1 << (index+1);
}
A[index] = y_bit;
- sink_cell->setPort(ID(A), A);
+ sink_cell->setPort(ID::A, A);
sink_cell->setParam(ID(LUT), mask);
}
@@ -798,10 +798,10 @@ clone_lut:
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}
auto cell = module->addLut(NEW_ID,
- driver_lut->getPort(ID(A)),
+ driver_lut->getPort(ID::A),
y_bit,
driver_mask);
- for (auto &bit : cell->connections_.at(ID(A))) {
+ for (auto &bit : cell->connections_.at(ID::A)) {
bit.wire = module->wires_.at(remap_name(bit.wire->name));
bit2sinks[bit].push_back(cell);
}
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 58ed47ccf..5b168d524 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -91,7 +91,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_sf() {
if (GetSize(cached_sf) == 0) {
- cached_sf = alu_cell->getPort(ID(Y));
+ cached_sf = alu_cell->getPort(ID::Y);
cached_sf = cached_sf[GetSize(cached_sf)-1];
}
return cached_sf;
@@ -134,7 +134,7 @@ struct AlumaccWorker
Macc::port_t new_port;
n->cell = cell;
- n->y = sigmap(cell->getPort(ID(Y)));
+ n->y = sigmap(cell->getPort(ID::Y));
n->users = 0;
for (auto bit : n->y)
@@ -142,7 +142,7 @@ struct AlumaccWorker
if (cell->type.in(ID($pos), ID($neg)))
{
- new_port.in_a = sigmap(cell->getPort(ID(A)));
+ new_port.in_a = sigmap(cell->getPort(ID::A));
new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
new_port.do_subtract = cell->type == ID($neg);
n->macc.ports.push_back(new_port);
@@ -150,12 +150,12 @@ struct AlumaccWorker
if (cell->type.in(ID($add), ID($sub)))
{
- new_port.in_a = sigmap(cell->getPort(ID(A)));
+ new_port.in_a = sigmap(cell->getPort(ID::A));
new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
new_port.do_subtract = false;
n->macc.ports.push_back(new_port);
- new_port.in_a = sigmap(cell->getPort(ID(B)));
+ new_port.in_a = sigmap(cell->getPort(ID::B));
new_port.is_signed = cell->getParam(ID(B_SIGNED)).as_bool();
new_port.do_subtract = cell->type == ID($sub);
n->macc.ports.push_back(new_port);
@@ -163,8 +163,8 @@ struct AlumaccWorker
if (cell->type.in(ID($mul)))
{
- new_port.in_a = sigmap(cell->getPort(ID(A)));
- new_port.in_b = sigmap(cell->getPort(ID(B)));
+ new_port.in_a = sigmap(cell->getPort(ID::A));
+ new_port.in_b = sigmap(cell->getPort(ID::B));
new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
new_port.do_subtract = false;
n->macc.ports.push_back(new_port);
@@ -361,7 +361,7 @@ struct AlumaccWorker
n->macc.optimize(GetSize(n->y));
n->macc.to_cell(cell);
- cell->setPort(ID(Y), n->y);
+ cell->setPort(ID::Y, n->y);
cell->fixup_parameters();
module->remove(n->cell);
delete n;
@@ -390,9 +390,9 @@ struct AlumaccWorker
bool cmp_equal = cell->type.in(ID($le), ID($ge));
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
- RTLIL::SigSpec A = sigmap(cell->getPort(ID(A)));
- RTLIL::SigSpec B = sigmap(cell->getPort(ID(B)));
- RTLIL::SigSpec Y = sigmap(cell->getPort(ID(Y)));
+ RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
+ RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
+ RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
if (B < A && GetSize(B)) {
cmp_less = !cmp_less;
@@ -430,9 +430,9 @@ struct AlumaccWorker
bool cmp_equal = cell->type.in(ID($eq), ID($eqx));
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
- RTLIL::SigSpec A = sigmap(cell->getPort(ID(A)));
- RTLIL::SigSpec B = sigmap(cell->getPort(ID(B)));
- RTLIL::SigSpec Y = sigmap(cell->getPort(ID(Y)));
+ RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
+ RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
+ RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
if (B < A && GetSize(B))
std::swap(A, B);
@@ -482,11 +482,11 @@ struct AlumaccWorker
if (n->cells.size() > 0)
n->alu_cell->set_src_attribute(n->cells[0]->get_src_attribute());
- n->alu_cell->setPort(ID(A), n->a);
- n->alu_cell->setPort(ID(B), n->b);
+ n->alu_cell->setPort(ID::A, n->a);
+ n->alu_cell->setPort(ID::B, n->b);
n->alu_cell->setPort(ID(CI), GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort(ID(BI), n->invert_b ? State::S1 : State::S0);
- n->alu_cell->setPort(ID(Y), n->y);
+ n->alu_cell->setPort(ID::Y, n->y);
n->alu_cell->setPort(ID(X), module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID(CO), module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
index 585732e6b..b976b401b 100644
--- a/passes/techmap/deminout.cc
+++ b/passes/techmap/deminout.cc
@@ -83,13 +83,13 @@ struct DeminoutPass : public Pass {
for (auto bit : sigmap(conn.second))
bits_used.insert(bit);
- if (conn.first == ID(Y) && cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_TBUF_), ID($tribuf)))
+ if (conn.first == ID::Y && cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_TBUF_), ID($tribuf)))
{
bool tribuf = cell->type.in(ID($_TBUF_), ID($tribuf));
if (!tribuf) {
for (auto &c : cell->connections()) {
- if (!c.first.in(ID(A), ID(B)))
+ if (!c.first.in(ID::A, ID::B))
continue;
for (auto b : sigmap(c.second))
if (b == State::Sz)
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 24760420a..e766f2cf6 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -53,7 +53,7 @@ struct Dff2dffeWorker
for (auto cell : module->cells()) {
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
- RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID(Y)));
+ RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i);
}
@@ -86,8 +86,8 @@ struct Dff2dffeWorker
return ret;
cell_int_t mux_cell_int = bit2mux.at(d);
- RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort(ID(A)));
- RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort(ID(B)));
+ RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort(ID::A));
+ RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort(ID::B));
RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID(S)));
int width = GetSize(sig_a), index = mux_cell_int.second;
@@ -97,9 +97,9 @@ struct Dff2dffeWorker
ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
if (sig_b[i*width + index] == q) {
- RTLIL::SigSpec s = mux_cell_int.first->getPort(ID(B));
+ RTLIL::SigSpec s = mux_cell_int.first->getPort(ID::B);
s[i*width + index] = RTLIL::Sx;
- mux_cell_int.first->setPort(ID(B), s);
+ mux_cell_int.first->setPort(ID::B, s);
}
return ret;
@@ -120,9 +120,9 @@ struct Dff2dffeWorker
ret.insert(pat);
if (sig_b[i*width + index] == q) {
- RTLIL::SigSpec s = mux_cell_int.first->getPort(ID(B));
+ RTLIL::SigSpec s = mux_cell_int.first->getPort(ID::B);
s[i*width + index] = RTLIL::Sx;
- mux_cell_int.first->setPort(ID(B), s);
+ mux_cell_int.first->setPort(ID::B, s);
}
}
@@ -130,9 +130,9 @@ struct Dff2dffeWorker
ret.insert(pat);
if (sig_a[index] == q) {
- RTLIL::SigSpec s = mux_cell_int.first->getPort(ID(A));
+ RTLIL::SigSpec s = mux_cell_int.first->getPort(ID::A);
s[index] = RTLIL::Sx;
- mux_cell_int.first->setPort(ID(A), s);
+ mux_cell_int.first->setPort(ID::A, s);
}
return ret;
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
index f74001b77..0ea033513 100644
--- a/passes/techmap/dff2dffs.cc
+++ b/passes/techmap/dff2dffs.cc
@@ -72,11 +72,11 @@ struct Dff2dffsPass : public Pass {
if (cell->type != ID($_MUX_))
continue;
- SigBit bit_a = sigmap(cell->getPort(ID(A)));
- SigBit bit_b = sigmap(cell->getPort(ID(B)));
+ SigBit bit_a = sigmap(cell->getPort(ID::A));
+ SigBit bit_b = sigmap(cell->getPort(ID::B));
if (bit_a.wire == nullptr || bit_b.wire == nullptr)
- sr_muxes[sigmap(cell->getPort(ID(Y)))] = cell;
+ sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
}
for (auto cell : ff_cells)
@@ -92,8 +92,8 @@ struct Dff2dffsPass : public Pass {
continue;
Cell *mux_cell = sr_muxes.at(bit_d);
- SigBit bit_a = sigmap(mux_cell->getPort(ID(A)));
- SigBit bit_b = sigmap(mux_cell->getPort(ID(B)));
+ SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
+ SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
SigBit bit_s = sigmap(mux_cell->getPort(ID(S)));
log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index c62224f9d..8a378068e 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -485,7 +485,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
cell_list.push_back(it.second);
if (it.second->type == ID($_NOT_))
- notmap[sigmap(it.second->getPort(ID(A)))].insert(it.second);
+ notmap[sigmap(it.second->getPort(ID::A))].insert(it.second);
}
std::map<std::string, int> stats;
@@ -519,8 +519,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
sig = module->addWire(NEW_ID, GetSize(old_sig));
if (has_q && has_qn) {
for (auto &it : notmap[sigmap(old_sig)]) {
- module->connect(it->getPort(ID(Y)), sig);
- it->setPort(ID(Y), module->addWire(NEW_ID, GetSize(old_sig)));
+ module->connect(it->getPort(ID::Y), sig);
+ it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig)));
}
} else {
module->addNotGate(NEW_ID, sig, old_sig);
diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc
index 2e50bb7b3..17a99493d 100644
--- a/passes/techmap/extract_counter.cc
+++ b/passes/techmap/extract_counter.cc
@@ -138,7 +138,7 @@ int counter_tryextract(
//To be a counter, one input of the ALU must be a constant 1
//TODO: can A or B be swapped in synthesized RTL or is B always the 1?
- const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID(B)));
+ const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
return 4;
@@ -158,7 +158,7 @@ int counter_tryextract(
//Y must have exactly one connection, and it has to be a $mux cell.
//We must have a direct bus connection from our Y to their A.
- const RTLIL::SigSpec aluy = sigmap(cell->getPort(ID(Y)));
+ const RTLIL::SigSpec aluy = sigmap(cell->getPort(ID::Y));
pool<Cell*> y_loads = get_other_cells(aluy, index, cell);
if(y_loads.size() != 1)
return 9;
@@ -166,11 +166,11 @@ int counter_tryextract(
extract.count_mux = count_mux;
if(count_mux->type != ID($mux))
return 10;
- if(!is_full_bus(aluy, index, cell, ID(Y), count_mux, ID(A)))
+ if(!is_full_bus(aluy, index, cell, ID::Y, count_mux, ID::A))
return 11;
//B connection of the mux is our underflow value
- const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID(B)));
+ const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B));
if(!underflow.is_fully_const())
return 12;
extract.count_value = underflow.as_int();
@@ -184,7 +184,7 @@ int counter_tryextract(
{
if(c->type != ID($logic_not))
continue;
- if(!is_full_bus(muxsel, index, c, ID(Y), count_mux, ID(S), true))
+ if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID(S), true))
continue;
underflow_inv = c;
@@ -196,7 +196,7 @@ int counter_tryextract(
//Y connection of the mux must have exactly one load, the counter's internal register, if there's no clock enable
//If we have a clock enable, Y drives the B input of a mux. A of that mux must come from our register
- const RTLIL::SigSpec muxy = sigmap(count_mux->getPort(ID(Y)));
+ const RTLIL::SigSpec muxy = sigmap(count_mux->getPort(ID::Y));
pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
if(muxy_loads.size() != 1)
return 14;
@@ -209,7 +209,7 @@ int counter_tryextract(
//This mux is probably a clock enable mux.
//Find our count register (should be our only load)
cemux = muxload;
- cey = sigmap(cemux->getPort(ID(Y)));
+ cey = sigmap(cemux->getPort(ID::Y));
pool<Cell*> cey_loads = get_other_cells(cey, index, cemux);
if(cey_loads.size() != 1)
return 24;
@@ -217,11 +217,11 @@ int counter_tryextract(
//Mux should have A driven by count Q, and B by muxy
//TODO: if A and B are swapped, CE polarity is inverted
- if(sigmap(cemux->getPort(ID(B))) != muxy)
+ if(sigmap(cemux->getPort(ID::B)) != muxy)
return 24;
- if(sigmap(cemux->getPort(ID(A))) != sigmap(count_reg->getPort(ID(Q))))
+ if(sigmap(cemux->getPort(ID::A)) != sigmap(count_reg->getPort(ID(Q))))
return 24;
- if(sigmap(cemux->getPort(ID(Y))) != sigmap(count_reg->getPort(ID(D))))
+ if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID(D))))
return 24;
//Select of the mux is our clock enable
@@ -260,12 +260,12 @@ int counter_tryextract(
//Sanity check that we use the ALU output properly
if(extract.has_ce)
{
- if(!is_full_bus(muxy, index, count_mux, ID(Y), cemux, ID(B)))
+ if(!is_full_bus(muxy, index, count_mux, ID::Y, cemux, ID::B))
return 16;
- if(!is_full_bus(cey, index, cemux, ID(Y), count_reg, ID(D)))
+ if(!is_full_bus(cey, index, cemux, ID::Y, count_reg, ID(D)))
return 16;
}
- else if(!is_full_bus(muxy, index, count_mux, ID(Y), count_reg, ID(D)))
+ else if(!is_full_bus(muxy, index, count_mux, ID::Y, count_reg, ID(D)))
return 16;
//TODO: Verify count_reg CLK_POLARITY is 1
@@ -312,9 +312,9 @@ int counter_tryextract(
}
}
}
- if(!is_full_bus(cnout, index, count_reg, ID(Q), underflow_inv, ID(A), true))
+ if(!is_full_bus(cnout, index, count_reg, ID(Q), underflow_inv, ID::A, true))
return 18;
- if(!is_full_bus(cnout, index, count_reg, ID(Q), cell, ID(A), true))
+ if(!is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true))
return 19;
//Look up the clock from the register
@@ -348,7 +348,7 @@ void counter_worker(
//A input is the count value. Check if it has COUNT_EXTRACT set.
//If it's not a wire, don't even try
- auto port = sigmap(cell->getPort(ID(A)));
+ auto port = sigmap(cell->getPort(ID::A));
if(!port.is_wire())
return;
RTLIL::Wire* a_wire = port.as_wire();
@@ -434,13 +434,13 @@ void counter_worker(
string countname = string("$COUNTx$") + log_id(extract.rwire->name.str());
//Wipe all of the old connections to the ALU
- cell->unsetPort(ID(A));
- cell->unsetPort(ID(B));
+ cell->unsetPort(ID::A);
+ cell->unsetPort(ID::B);
cell->unsetPort(ID(BI));
cell->unsetPort(ID(CI));
cell->unsetPort(ID(CO));
cell->unsetPort(ID(X));
- cell->unsetPort(ID(Y));
+ cell->unsetPort(ID::Y);
cell->unsetParam(ID(A_SIGNED));
cell->unsetParam(ID(A_WIDTH));
cell->unsetParam(ID(B_SIGNED));
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc
index ff3de1272..29700c37b 100644
--- a/passes/techmap/extract_fa.cc
+++ b/passes/techmap/extract_fa.cc
@@ -89,7 +89,7 @@ struct ExtractFaWorker
ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
{
- SigBit y = sigmap(SigBit(cell->getPort(ID(Y))));
+ SigBit y = sigmap(SigBit(cell->getPort(ID::Y)));
log_assert(driver.count(y) == 0);
driver[y] = cell;
}
@@ -262,8 +262,8 @@ struct ExtractFaWorker
pool<SigBit> new_leaves = leaves;
new_leaves.erase(bit);
- if (cell->hasPort(ID(A))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(A)))));
- if (cell->hasPort(ID(B))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(B)))));
+ if (cell->hasPort(ID::A)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::A))));
+ if (cell->hasPort(ID::B)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::B))));
if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C)))));
if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D)))));
@@ -277,8 +277,8 @@ struct ExtractFaWorker
void assign_new_driver(SigBit bit, SigBit new_driver)
{
Cell *cell = driver.at(bit);
- if (sigmap(cell->getPort(ID(Y))) == bit) {
- cell->setPort(ID(Y), module->addWire(NEW_ID));
+ if (sigmap(cell->getPort(ID::Y)) == bit) {
+ cell->setPort(ID::Y, module->addWire(NEW_ID));
module->connect(bit, new_driver);
}
}
@@ -395,15 +395,15 @@ struct ExtractFaWorker
log(" Created $fa cell %s.\n", log_id(cell));
- cell->setPort(ID(A), f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
- cell->setPort(ID(B), f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
+ cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
+ cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID(C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
cell->setPort(ID(X), X);
- cell->setPort(ID(Y), Y);
+ cell->setPort(ID::Y, Y);
facache[fakey] = make_tuple(X, Y, cell);
}
@@ -501,15 +501,15 @@ struct ExtractFaWorker
log(" Created $fa cell %s.\n", log_id(cell));
- cell->setPort(ID(A), f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
- cell->setPort(ID(B), f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
+ cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
+ cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID(C), State::S0);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
cell->setPort(ID(X), X);
- cell->setPort(ID(Y), Y);
+ cell->setPort(ID::Y, Y);
}
if (func2.at(key).count(xor2_func)) {
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index 2ce111b4f..11cfddcd9 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -148,7 +148,7 @@ struct ExtractReducePass : public Pass
head_cell = x;
- auto y = sigmap(x->getPort(ID(Y)));
+ auto y = sigmap(x->getPort(ID::Y));
log_assert(y.size() == 1);
// Should only continue if there is one fanout back into a cell (not to a port)
@@ -166,7 +166,7 @@ struct ExtractReducePass : public Pass
{
//BFS, following all chains until they hit a cell of a different type
//Pick the longest one
- auto y = sigmap(cell->getPort(ID(Y)));
+ auto y = sigmap(cell->getPort(ID::Y));
pool<Cell*> current_loads = sig_to_sink[y];
pool<Cell*> next_loads;
@@ -233,7 +233,7 @@ struct ExtractReducePass : public Pass
cur_supercell.insert(x);
- auto a = sigmap(x->getPort(ID(A)));
+ auto a = sigmap(x->getPort(ID::A));
log_assert(a.size() == 1);
// Must have only one sink unless we're going off chain
@@ -249,7 +249,7 @@ struct ExtractReducePass : public Pass
}
}
- auto b = sigmap(x->getPort(ID(B)));
+ auto b = sigmap(x->getPort(ID::B));
log_assert(b.size() == 1);
// Must have only one sink
@@ -279,16 +279,16 @@ struct ExtractReducePass : public Pass
pool<SigBit> input_pool_intermed;
for (auto x : cur_supercell)
{
- input_pool.insert(sigmap(x->getPort(ID(A)))[0]);
- input_pool.insert(sigmap(x->getPort(ID(B)))[0]);
- input_pool_intermed.insert(sigmap(x->getPort(ID(Y)))[0]);
+ input_pool.insert(sigmap(x->getPort(ID::A))[0]);
+ input_pool.insert(sigmap(x->getPort(ID::B))[0]);
+ input_pool_intermed.insert(sigmap(x->getPort(ID::Y))[0]);
}
SigSpec input;
for (auto b : input_pool)
if (input_pool_intermed.count(b) == 0)
input.append_bit(b);
- SigBit output = sigmap(head_cell->getPort(ID(Y))[0]);
+ SigBit output = sigmap(head_cell->getPort(ID::Y)[0]);
auto new_reduce_cell = module->addCell(NEW_ID,
gt == GateType::And ? ID($reduce_and) :
@@ -297,8 +297,8 @@ struct ExtractReducePass : public Pass
new_reduce_cell->setParam(ID(A_SIGNED), 0);
new_reduce_cell->setParam(ID(A_WIDTH), input.size());
new_reduce_cell->setParam(ID(Y_WIDTH), 1);
- new_reduce_cell->setPort(ID(A), input);
- new_reduce_cell->setPort(ID(Y), output);
+ new_reduce_cell->setPort(ID::A, input);
+ new_reduce_cell->setPort(ID::Y, output);
if(allow_off_chain)
consumed_cells.insert(head_cell);
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 726fcb905..898cb77a4 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -180,7 +180,7 @@ struct IopadmapPass : public Pass {
for (auto cell : module->cells())
if (cell->type == ID($_TBUF_)) {
- SigBit bit = sigmap(cell->getPort(ID(Y)).as_bit());
+ SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
tbuf_bits[bit].first = cell->name;
}
@@ -213,7 +213,7 @@ struct IopadmapPass : public Pass {
continue;
SigBit en_sig = tbuf_cell->getPort(ID(E)).as_bit();
- SigBit data_sig = tbuf_cell->getPort(ID(A)).as_bit();
+ SigBit data_sig = tbuf_cell->getPort(ID::A).as_bit();
if (wire->port_input && !tinoutpad_celltype.empty())
{
diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc
index 6877a75e2..c6618fc9d 100644
--- a/passes/techmap/lut2mux.cc
+++ b/passes/techmap/lut2mux.cc
@@ -25,8 +25,8 @@ PRIVATE_NAMESPACE_BEGIN
int lut2mux(Cell *cell)
{
- SigSpec sig_a = cell->getPort(ID(A));
- SigSpec sig_y = cell->getPort(ID(Y));
+ SigSpec sig_a = cell->getPort(ID::A);
+ SigSpec sig_y = cell->getPort(ID::Y);
Const lut = cell->getParam(ID(LUT));
int count = 1;
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index 616ff21f2..09f61927c 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -113,10 +113,10 @@ struct MaccmapWorker
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID(WIDTH), width);
- cell->setPort(ID(A), in1);
- cell->setPort(ID(B), in2);
+ cell->setPort(ID::A, in1);
+ cell->setPort(ID::B, in2);
cell->setPort(ID(C), in3);
- cell->setPort(ID(Y), w1);
+ cell->setPort(ID::Y, w1);
cell->setPort(ID(X), w2);
out1 = {out_zeros_msb, w1, out_zeros_lsb};
@@ -238,11 +238,11 @@ struct MaccmapWorker
RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu));
- c->setPort(ID(A), summands.front());
- c->setPort(ID(B), summands.back());
+ c->setPort(ID::A, summands.front());
+ c->setPort(ID::B, summands.back());
c->setPort(ID(CI), State::S0);
c->setPort(ID(BI), State::S0);
- c->setPort(ID(Y), module->addWire(NEW_ID, width));
+ c->setPort(ID::Y, module->addWire(NEW_ID, width));
c->setPort(ID(X), module->addWire(NEW_ID, width));
c->setPort(ID(CO), module->addWire(NEW_ID, width));
c->fixup_parameters();
@@ -253,7 +253,7 @@ struct MaccmapWorker
}
log_assert(tree_sum_bits.empty());
- return c->getPort(ID(Y));
+ return c->getPort(ID::Y);
}
};
@@ -264,17 +264,17 @@ extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false
void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
{
- int width = GetSize(cell->getPort(ID(Y)));
+ int width = GetSize(cell->getPort(ID::Y));
Macc macc;
macc.from_cell(cell);
RTLIL::SigSpec all_input_bits;
- all_input_bits.append(cell->getPort(ID(A)));
- all_input_bits.append(cell->getPort(ID(B)));
+ all_input_bits.append(cell->getPort(ID::A));
+ all_input_bits.append(cell->getPort(ID::B));
if (all_input_bits.to_sigbit_set().count(RTLIL::Sx)) {
- module->connect(cell->getPort(ID(Y)), RTLIL::SigSpec(RTLIL::Sx, width));
+ module->connect(cell->getPort(ID::Y), RTLIL::SigSpec(RTLIL::Sx, width));
return;
}
@@ -339,9 +339,9 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
}
if (summands.front().second)
- module->addNeg(NEW_ID, summands.front().first, cell->getPort(ID(Y)));
+ module->addNeg(NEW_ID, summands.front().first, cell->getPort(ID::Y));
else
- module->connect(cell->getPort(ID(Y)), summands.front().first);
+ module->connect(cell->getPort(ID::Y), summands.front().first);
}
else
{
@@ -356,7 +356,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (auto &bit : macc.bit_ports)
worker.add(bit, 0);
- module->connect(cell->getPort(ID(Y)), worker.synth());
+ module->connect(cell->getPort(ID::Y), worker.synth());
}
}
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index 64d5b4f7b..5541b6122 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -122,7 +122,7 @@ struct MuxcoverWorker
}
}
if (cell->type == ID($_MUX_))
- sig_to_mux[sigmap(cell->getPort(ID(Y)))] = cell;
+ sig_to_mux[sigmap(cell->getPort(ID::Y))] = cell;
}
log(" Treeifying %d MUXes:\n", GetSize(sig_to_mux));
@@ -141,8 +141,8 @@ struct MuxcoverWorker
if (sig_to_mux.count(bit) && (bit == rootsig || !roots.count(bit))) {
Cell *c = sig_to_mux.at(bit);
tree.muxes[bit] = c;
- wavefront.insert(sigmap(c->getPort(ID(A))));
- wavefront.insert(sigmap(c->getPort(ID(B))));
+ wavefront.insert(sigmap(c->getPort(ID::A)));
+ wavefront.insert(sigmap(c->getPort(ID::B)));
}
}
@@ -517,31 +517,31 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 2) {
count_muxes_by_type[0]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
- cell->setPort(ID(A), mux.inputs[0]);
- cell->setPort(ID(B), mux.inputs[1]);
+ cell->setPort(ID::A, mux.inputs[0]);
+ cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID(S), mux.selects[0]);
- cell->setPort(ID(Y), bit);
+ cell->setPort(ID::Y, bit);
return;
}
if (GetSize(mux.inputs) == 4) {
count_muxes_by_type[1]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
- cell->setPort(ID(A), mux.inputs[0]);
- cell->setPort(ID(B), mux.inputs[1]);
+ cell->setPort(ID::A, mux.inputs[0]);
+ cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID(C), mux.inputs[2]);
cell->setPort(ID(D), mux.inputs[3]);
cell->setPort(ID(S), mux.selects[0]);
cell->setPort(ID(T), mux.selects[1]);
- cell->setPort(ID(Y), bit);
+ cell->setPort(ID::Y, bit);
return;
}
if (GetSize(mux.inputs) == 8) {
count_muxes_by_type[2]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
- cell->setPort(ID(A), mux.inputs[0]);
- cell->setPort(ID(B), mux.inputs[1]);
+ cell->setPort(ID::A, mux.inputs[0]);
+ cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID(C), mux.inputs[2]);
cell->setPort(ID(D), mux.inputs[3]);
cell->setPort(ID(E), mux.inputs[4]);
@@ -551,15 +551,15 @@ struct MuxcoverWorker
cell->setPort(ID(S), mux.selects[0]);
cell->setPort(ID(T), mux.selects[1]);
cell->setPort(ID(U), mux.selects[2]);
- cell->setPort(ID(Y), bit);
+ cell->setPort(ID::Y, bit);
return;
}
if (GetSize(mux.inputs) == 16) {
count_muxes_by_type[3]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
- cell->setPort(ID(A), mux.inputs[0]);
- cell->setPort(ID(B), mux.inputs[1]);
+ cell->setPort(ID::A, mux.inputs[0]);
+ cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID(C), mux.inputs[2]);
cell->setPort(ID(D), mux.inputs[3]);
cell->setPort(ID(E), mux.inputs[4]);
@@ -578,7 +578,7 @@ struct MuxcoverWorker
cell->setPort(ID(T), mux.selects[1]);
cell->setPort(ID(U), mux.selects[2]);
cell->setPort(ID(V), mux.selects[3]);
- cell->setPort(ID(Y), bit);
+ cell->setPort(ID::Y, bit);
return;
}
diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc
index 4a3428b3c..798d82248 100644
--- a/passes/techmap/nlutmap.cc
+++ b/passes/techmap/nlutmap.cc
@@ -85,7 +85,7 @@ struct NlutmapWorker
if (cell->type != ID($lut) || mapped_cells.count(cell))
continue;
- if (GetSize(cell->getPort(ID(A))) == lut_size || lut_size == 2)
+ if (GetSize(cell->getPort(ID::A)) == lut_size || lut_size == 2)
candidate_ratings[cell] = 0;
for (auto &conn : cell->connections())
diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc
index f77652f3b..31ab13cec 100644
--- a/passes/techmap/pmuxtree.cc
+++ b/passes/techmap/pmuxtree.cc
@@ -92,18 +92,18 @@ struct PmuxtreePass : public Pass {
if (cell->type != ID($pmux))
continue;
- SigSpec sig_data = cell->getPort(ID(B));
+ SigSpec sig_data = cell->getPort(ID::B);
SigSpec sig_sel = cell->getPort(ID(S));
- if (!cell->getPort(ID(A)).is_fully_undef()) {
- sig_data.append(cell->getPort(ID(A)));
+ if (!cell->getPort(ID::A).is_fully_undef()) {
+ sig_data.append(cell->getPort(ID::A));
SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel);
sig_sel.append(module->Not(NEW_ID, sig_sel_or));
}
SigSpec result, result_or;
result = recursive_mux_generator(module, sig_data, sig_sel, result_or);
- module->connect(cell->getPort(ID(Y)), result);
+ module->connect(cell->getPort(ID::Y), result);
module->remove(cell);
}
}
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 92637dfa8..cb877c2f4 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -107,16 +107,16 @@ struct ShregmapTechXilinx7 : ShregmapTech
if (cell->type == ID($shiftx)) {
if (cell->getParam(ID(Y_WIDTH)) != 1) continue;
int j = 0;
- for (auto bit : sigmap(cell->getPort(ID(A))))
+ for (auto bit : sigmap(cell->getPort(ID::A)))
sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
log_assert(j == cell->getParam(ID(A_WIDTH)).as_int());
}
else if (cell->type == ID($mux)) {
int j = 0;
- for (auto bit : sigmap(cell->getPort(ID(A))))
+ for (auto bit : sigmap(cell->getPort(ID::A)))
sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
j = 0;
- for (auto bit : sigmap(cell->getPort(ID(B))))
+ for (auto bit : sigmap(cell->getPort(ID::B)))
sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
}
}
@@ -128,9 +128,9 @@ struct ShregmapTechXilinx7 : ShregmapTech
if (it == sigbit_to_shiftx_offset.end())
return;
if (cell) {
- if (cell->type == ID($shiftx) && port == ID(A))
+ if (cell->type == ID($shiftx) && port == ID::A)
return;
- if (cell->type == ID($mux) && port.in(ID(A), ID(B)))
+ if (cell->type == ID($mux) && port.in(ID::A, ID::B))
return;
}
sigbit_to_shiftx_offset.erase(it);
@@ -183,7 +183,7 @@ struct ShregmapTechXilinx7 : ShregmapTech
// Due to padding the most significant bits of A may be 1'bx,
// and if so, discount them
if (GetSize(taps) < shiftx->getParam(ID(A_WIDTH)).as_int()) {
- const SigSpec A = shiftx->getPort(ID(A));
+ const SigSpec A = shiftx->getPort(ID::A);
const int A_width = shiftx->getParam(ID(A_WIDTH)).as_int();
for (int i = GetSize(taps); i < A_width; ++i)
if (A[i] != RTLIL::Sx) return false;
@@ -223,14 +223,14 @@ struct ShregmapTechXilinx7 : ShregmapTech
Cell* shiftx = std::get<0>(it->second);
RTLIL::SigSpec l_wire, q_wire;
if (shiftx->type == ID($shiftx)) {
- l_wire = shiftx->getPort(ID(B));
- q_wire = shiftx->getPort(ID(Y));
- shiftx->setPort(ID(Y), cell->module->addWire(NEW_ID));
+ l_wire = shiftx->getPort(ID::B);
+ q_wire = shiftx->getPort(ID::Y);
+ shiftx->setPort(ID::Y, cell->module->addWire(NEW_ID));
}
else if (shiftx->type == ID($mux)) {
l_wire = shiftx->getPort(ID(S));
- q_wire = shiftx->getPort(ID(Y));
- shiftx->setPort(ID(Y), cell->module->addWire(NEW_ID));
+ q_wire = shiftx->getPort(ID::Y);
+ shiftx->setPort(ID::Y, cell->module->addWire(NEW_ID));
}
else log_abort();
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 325a816ee..91574f3c6 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -28,23 +28,23 @@ YOSYS_NAMESPACE_BEGIN
void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), sig_a[i]);
- gate->setPort(ID(Y), sig_y[i]);
+ gate->setPort(ID::A, sig_a[i]);
+ gate->setPort(ID::Y, sig_y[i]);
}
}
void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
@@ -53,9 +53,9 @@ void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_b = cell->getPort(ID(B));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_b = cell->getPort(ID::B);
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID(B_SIGNED)).as_bool());
@@ -67,8 +67,8 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), sig_t[i]);
- gate->setPort(ID(Y), sig_y[i]);
+ gate->setPort(ID::A, sig_t[i]);
+ gate->setPort(ID::Y, sig_y[i]);
}
sig_y = sig_t;
@@ -84,16 +84,16 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), sig_a[i]);
- gate->setPort(ID(B), sig_b[i]);
- gate->setPort(ID(Y), sig_y[i]);
+ gate->setPort(ID::A, sig_a[i]);
+ gate->setPort(ID::B, sig_b[i]);
+ gate->setPort(ID::Y, sig_y[i]);
}
}
void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
if (sig_y.size() == 0)
return;
@@ -135,9 +135,9 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), sig_a[i]);
- gate->setPort(ID(B), sig_a[i+1]);
- gate->setPort(ID(Y), sig_t[i/2]);
+ gate->setPort(ID::A, sig_a[i]);
+ gate->setPort(ID::B, sig_a[i+1]);
+ gate->setPort(ID::Y, sig_t[i/2]);
last_output_cell = gate;
}
@@ -148,8 +148,8 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), sig_a);
- gate->setPort(ID(Y), sig_t);
+ gate->setPort(ID::A, sig_a);
+ gate->setPort(ID::Y, sig_t);
last_output_cell = gate;
sig_a = sig_t;
}
@@ -157,7 +157,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
if (last_output_cell == NULL) {
module->connect(RTLIL::SigSig(sig_y, sig_a));
} else {
- last_output_cell->setPort(ID(Y), sig_y);
+ last_output_cell->setPort(ID::Y, sig_y);
}
}
@@ -176,9 +176,9 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), sig[i]);
- gate->setPort(ID(B), sig[i+1]);
- gate->setPort(ID(Y), sig_t[i/2]);
+ gate->setPort(ID::A, sig[i]);
+ gate->setPort(ID::B, sig[i+1]);
+ gate->setPort(ID::Y, sig_t[i/2]);
}
sig = sig_t;
@@ -190,10 +190,10 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
logic_reduce(module, sig_a, cell);
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
if (sig_y.size() == 0)
return;
@@ -205,19 +205,19 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), sig_a);
- gate->setPort(ID(Y), sig_y);
+ gate->setPort(ID::A, sig_a);
+ gate->setPort(ID::Y, sig_y);
}
void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
logic_reduce(module, sig_a, cell);
- RTLIL::SigSpec sig_b = cell->getPort(ID(B));
+ RTLIL::SigSpec sig_b = cell->getPort(ID::B);
logic_reduce(module, sig_b, cell);
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
if (sig_y.size() == 0)
return;
@@ -234,16 +234,16 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), sig_a);
- gate->setPort(ID(B), sig_b);
- gate->setPort(ID(Y), sig_y);
+ gate->setPort(ID::A, sig_a);
+ gate->setPort(ID::B, sig_b);
+ gate->setPort(ID::Y, sig_y);
}
void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_b = cell->getPort(ID(B));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_b = cell->getPort(ID::B);
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
bool is_signed = cell->parameters.at(ID(A_SIGNED)).as_bool();
bool is_ne = cell->type.in(ID($ne), ID($nex));
@@ -269,38 +269,38 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_b = cell->getPort(ID(B));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_b = cell->getPort(ID::B);
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), sig_a[i]);
- gate->setPort(ID(B), sig_b[i]);
+ gate->setPort(ID::A, sig_a[i]);
+ gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID(S), cell->getPort(ID(S)));
- gate->setPort(ID(Y), sig_y[i]);
+ gate->setPort(ID::Y, sig_y[i]);
}
}
void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_e = cell->getPort(ID(EN));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), sig_a[i]);
+ gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID(E), sig_e);
- gate->setPort(ID(Y), sig_y[i]);
+ gate->setPort(ID::Y, sig_y[i]);
}
}
void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
{
- SigSpec lut_ctrl = cell->getPort(ID(A));
+ SigSpec lut_ctrl = cell->getPort(ID::A);
SigSpec lut_data = cell->getParam(ID(LUT));
lut_data.extend_u0(1 << cell->getParam(ID(WIDTH)).as_int());
@@ -310,20 +310,20 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(A), lut_data[i]);
- gate->setPort(ID(B), lut_data[i+1]);
+ gate->setPort(ID::A, lut_data[i]);
+ gate->setPort(ID::B, lut_data[i+1]);
gate->setPort(ID(S), lut_ctrl[idx]);
- gate->setPort(ID(Y), new_lut_data[i/2]);
+ gate->setPort(ID::Y, new_lut_data[i/2]);
}
lut_data = new_lut_data;
}
- module->connect(cell->getPort(ID(Y)), lut_data);
+ module->connect(cell->getPort(ID::Y), lut_data);
}
void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
{
- SigSpec ctrl = cell->getPort(ID(A));
+ SigSpec ctrl = cell->getPort(ID::A);
SigSpec table = cell->getParam(ID(TABLE));
int width = cell->getParam(ID(WIDTH)).as_int();
@@ -348,22 +348,22 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1);
}
- module->connect(cell->getPort(ID(Y)), module->ReduceOr(NEW_ID, products));
+ module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID, products));
}
void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
{
int offset = cell->parameters.at(ID(OFFSET)).as_int();
- RTLIL::SigSpec sig_a = cell->getPort(ID(A));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
}
void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_ab = cell->getPort(ID(A));
- sig_ab.append(cell->getPort(ID(B)));
- RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
+ RTLIL::SigSpec sig_ab = cell->getPort(ID::A);
+ sig_ab.append(cell->getPort(ID::B));
+ RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
module->connect(RTLIL::SigSig(sig_y, sig_ab));
}
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index e81dc33ee..fa038c1b9 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -520,7 +520,7 @@ struct TechmapWorker
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
- if (w->name.in(ID(Y), ID(Q)))
+ if (w->name.in(ID::Y, ID(Q)))
w->port_output = true;
else
w->port_input = true;
diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc
index 509a9198b..41fdc8f3d 100644
--- a/passes/techmap/tribuf.cc
+++ b/passes/techmap/tribuf.cc
@@ -64,37 +64,37 @@ struct TribufWorker {
for (auto cell : module->selected_cells())
{
if (cell->type == ID($tribuf))
- tribuf_cells[sigmap(cell->getPort(ID(Y)))].push_back(cell);
+ tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
if (cell->type == ID($_TBUF_))
- tribuf_cells[sigmap(cell->getPort(ID(Y)))].push_back(cell);
+ tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
if (cell->type.in(ID($mux), ID($_MUX_)))
{
IdString en_port = cell->type == ID($mux) ? ID(EN) : ID(E);
IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_);
- if (is_all_z(cell->getPort(ID(A))) && is_all_z(cell->getPort(ID(B)))) {
+ if (is_all_z(cell->getPort(ID::A)) && is_all_z(cell->getPort(ID::B))) {
module->remove(cell);
continue;
}
- if (is_all_z(cell->getPort(ID(A)))) {
- cell->setPort(ID(A), cell->getPort(ID(B)));
+ if (is_all_z(cell->getPort(ID::A))) {
+ cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(en_port, cell->getPort(ID(S)));
- cell->unsetPort(ID(B));
+ cell->unsetPort(ID::B);
cell->unsetPort(ID(S));
cell->type = tri_type;
- tribuf_cells[sigmap(cell->getPort(ID(Y)))].push_back(cell);
+ tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
continue;
}
- if (is_all_z(cell->getPort(ID(B)))) {
+ if (is_all_z(cell->getPort(ID::B))) {
cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID(S))));
- cell->unsetPort(ID(B));
+ cell->unsetPort(ID::B);
cell->unsetPort(ID(S));
cell->type = tri_type;
- tribuf_cells[sigmap(cell->getPort(ID(Y)))].push_back(cell);
+ tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
continue;
}
}
@@ -122,7 +122,7 @@ struct TribufWorker {
pmux_s.append(cell->getPort(ID(EN)));
else
pmux_s.append(cell->getPort(ID(E)));
- pmux_b.append(cell->getPort(ID(A)));
+ pmux_b.append(cell->getPort(ID::A));
module->remove(cell);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-04 03:23:03 +0000