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-rw-r--r--passes/pmgen/xilinx_dsp.cc5
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 9291c2dfb..16a098fd0 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -83,9 +83,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
A.replace(Q, D);
if (st.ffAmux) {
SigSpec Y = st.ffAmux->getPort("\\Y");
- SigSpec AB = st.ffAmux->getPort(st.ffAmuxAB == "\\A" ? "\\B" : "\\A");
+ SigSpec AB = st.ffAmux->getPort(st.ffAenpol ? "\\A" : "\\B");
A.replace(Y, AB);
- cell->setPort("\\CEA2", st.ffAmux->getPort("\\S"));
+ SigSpec S = st.ffAmux->getPort("\\S");
+ cell->setPort("\\CEA2", st.ffAenpol ? S : pm.module->Not(NEW_ID, S));
}
else
cell->setPort("\\CEA2", State::S1);