29 files changed, 9 insertions, 9 deletions
diff --git a/manual/FILES_Eval/grep-it.sh b/manual/CHAPTER_Eval/grep-it.sh
index f92eb52cf..f92eb52cf 100644
--- a/manual/FILES_Eval/grep-it.sh
+++ b/manual/CHAPTER_Eval/grep-it.sh
diff --git a/manual/FILES_Eval/openmsp430.prj b/manual/CHAPTER_Eval/openmsp430.prj
index cb8cd2714..cb8cd2714 100644
--- a/manual/FILES_Eval/openmsp430.prj
+++ b/manual/CHAPTER_Eval/openmsp430.prj
diff --git a/manual/FILES_Eval/openmsp430_ys.prj b/manual/CHAPTER_Eval/openmsp430_ys.prj
index 0009c99dc..0009c99dc 100644
--- a/manual/FILES_Eval/openmsp430_ys.prj
+++ b/manual/CHAPTER_Eval/openmsp430_ys.prj
diff --git a/manual/FILES_Eval/or1200.prj b/manual/CHAPTER_Eval/or1200.prj
index 9496874e0..9496874e0 100644
--- a/manual/FILES_Eval/or1200.prj
+++ b/manual/CHAPTER_Eval/or1200.prj
diff --git a/manual/FILES_Eval/or1200_ys.prj b/manual/CHAPTER_Eval/or1200_ys.prj
index 4dd5f41a0..4dd5f41a0 100644
--- a/manual/FILES_Eval/or1200_ys.prj
+++ b/manual/CHAPTER_Eval/or1200_ys.prj
diff --git a/manual/FILES_Eval/run-it.sh b/manual/CHAPTER_Eval/run-it.sh
index b4a67cebd..b4a67cebd 100644
--- a/manual/FILES_Eval/run-it.sh
+++ b/manual/CHAPTER_Eval/run-it.sh
diff --git a/manual/FILES_Eval/settings.xst b/manual/CHAPTER_Eval/settings.xst
index 2f381d09d..2f381d09d 100644
--- a/manual/FILES_Eval/settings.xst
+++ b/manual/CHAPTER_Eval/settings.xst
diff --git a/manual/CHAPTER_Prog.tex b/manual/CHAPTER_Prog.tex
index b6157aa1c..3918594a2 100644
--- a/manual/CHAPTER_Prog.tex
+++ b/manual/CHAPTER_Prog.tex
@@ -13,9 +13,9 @@ with an example module.
 
 \section{Example Module}
 
-\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{FILES_Prog/stubnets.cc}
+\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{CHAPTER_Prog/stubnets.cc}
 
-\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{FILES_Prog/Makefile}
+\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{CHAPTER_Prog/Makefile}
 
-\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{FILES_Prog/test.v}
+\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{CHAPTER_Prog/test.v}
 
diff --git a/manual/FILES_Prog/Makefile b/manual/CHAPTER_Prog/Makefile
index 8e326bdc2..8e326bdc2 100644
--- a/manual/FILES_Prog/Makefile
+++ b/manual/CHAPTER_Prog/Makefile
diff --git a/manual/FILES_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index 1c71f78b8..1c71f78b8 100644
--- a/manual/FILES_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
diff --git a/manual/FILES_Prog/test.v b/manual/CHAPTER_Prog/test.v
index 201f75006..201f75006 100644
--- a/manual/FILES_Prog/test.v
+++ b/manual/CHAPTER_Prog/test.v
diff --git a/manual/CHAPTER_StateOfTheArt.tex b/manual/CHAPTER_StateOfTheArt.tex
index d6a5c9b18..7e62230ef 100644
--- a/manual/CHAPTER_StateOfTheArt.tex
+++ b/manual/CHAPTER_StateOfTheArt.tex
@@ -55,18 +55,18 @@ with a summary of the results.
 
 \begin{figure}[t!]
 	\begin{minipage}{7.7cm}
-		\lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/always01_pub.v}
+		\lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always01_pub.v}
 	\end{minipage}
 	\hfill
 	\begin{minipage}{7.7cm}
-		\lstinputlisting[frame=single,language=Verilog]{FILES_StateOfTheArt/always02_pub.v}
+		\lstinputlisting[frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always02_pub.v}
 	\end{minipage}
 	\caption{1st and 2nd Verilog always examples}
 	\label{fig:StateOfTheArt_always12}
 \end{figure}
 
 \begin{figure}[!]
-	\lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/always03.v}
+	\lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always03.v}
 	\caption{3rd Verilog always example}
 	\label{fig:StateOfTheArt_always3}
 \end{figure}
@@ -107,7 +107,7 @@ The first example is only using the most fundamental Verilog features. All
 tools under test were able to successfully synthesize this design.
 
 \begin{figure}[b!]
-	\lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/arrays01.v}
+	\lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/arrays01.v}
 	\caption{Verilog array example}
 	\label{fig:StateOfTheArt_arrays}
 \end{figure}
@@ -155,7 +155,7 @@ For this design HANA, vl2m and ODIN-II generate error messages indicating that
 arrays are not supported.
 
 \begin{figure}[t!]
-	\lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/forgen01.v}
+	\lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/forgen01.v}
 	\caption{Verilog for loop example}
 	\label{fig:StateOfTheArt_for}
 \end{figure}
@@ -171,7 +171,7 @@ by continuing tests on this aspect of Verilog synthesis such as synthesis of dua
 memories, correct handling of write collisions, and so forth.
 
 \begin{figure}[t!]
-	\lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/forgen02.v}
+	\lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/forgen02.v}
 	\caption{Verilog generate example}
 	\label{fig:StateOfTheArt_gen}
 \end{figure}
diff --git a/manual/FILES_StateOfTheArt/always01.v b/manual/CHAPTER_StateOfTheArt/always01.v
index 4719ed47e..4719ed47e 100644
--- a/manual/FILES_StateOfTheArt/always01.v
+++ b/manual/CHAPTER_StateOfTheArt/always01.v
diff --git a/manual/FILES_StateOfTheArt/always01_pub.v b/manual/CHAPTER_StateOfTheArt/always01_pub.v
index 6a6a4b231..6a6a4b231 100644
--- a/manual/FILES_StateOfTheArt/always01_pub.v
+++ b/manual/CHAPTER_StateOfTheArt/always01_pub.v
diff --git a/manual/FILES_StateOfTheArt/always02.v b/manual/CHAPTER_StateOfTheArt/always02.v
index 63f1ce317..63f1ce317 100644
--- a/manual/FILES_StateOfTheArt/always02.v
+++ b/manual/CHAPTER_StateOfTheArt/always02.v
diff --git a/manual/FILES_StateOfTheArt/always02_pub.v b/manual/CHAPTER_StateOfTheArt/always02_pub.v
index 91f1ca16d..91f1ca16d 100644
--- a/manual/FILES_StateOfTheArt/always02_pub.v
+++ b/manual/CHAPTER_StateOfTheArt/always02_pub.v
diff --git a/manual/FILES_StateOfTheArt/always03.v b/manual/CHAPTER_StateOfTheArt/always03.v
index 53386acd6..53386acd6 100644
--- a/manual/FILES_StateOfTheArt/always03.v
+++ b/manual/CHAPTER_StateOfTheArt/always03.v
diff --git a/manual/FILES_StateOfTheArt/arrays01.v b/manual/CHAPTER_StateOfTheArt/arrays01.v
index bd0eda294..bd0eda294 100644
--- a/manual/FILES_StateOfTheArt/arrays01.v
+++ b/manual/CHAPTER_StateOfTheArt/arrays01.v
diff --git a/manual/FILES_StateOfTheArt/cmp_tbdata.c b/manual/CHAPTER_StateOfTheArt/cmp_tbdata.c
index b188144dd..b188144dd 100644
--- a/manual/FILES_StateOfTheArt/cmp_tbdata.c
+++ b/manual/CHAPTER_StateOfTheArt/cmp_tbdata.c
diff --git a/manual/FILES_StateOfTheArt/forgen01.v b/manual/CHAPTER_StateOfTheArt/forgen01.v
index 70ee7e667..70ee7e667 100644
--- a/manual/FILES_StateOfTheArt/forgen01.v
+++ b/manual/CHAPTER_StateOfTheArt/forgen01.v
diff --git a/manual/FILES_StateOfTheArt/forgen02.v b/manual/CHAPTER_StateOfTheArt/forgen02.v
index 14af070c3..14af070c3 100644
--- a/manual/FILES_StateOfTheArt/forgen02.v
+++ b/manual/CHAPTER_StateOfTheArt/forgen02.v
diff --git a/manual/FILES_StateOfTheArt/iverilog-0.8.7-buildfixes.patch b/manual/CHAPTER_StateOfTheArt/iverilog-0.8.7-buildfixes.patch
index 63a03e595..63a03e595 100644
--- a/manual/FILES_StateOfTheArt/iverilog-0.8.7-buildfixes.patch
+++ b/manual/CHAPTER_StateOfTheArt/iverilog-0.8.7-buildfixes.patch
diff --git a/manual/FILES_StateOfTheArt/mvsis-1.3.6-buildfixes.patch b/manual/CHAPTER_StateOfTheArt/mvsis-1.3.6-buildfixes.patch
index 4b44320f8..4b44320f8 100644
--- a/manual/FILES_StateOfTheArt/mvsis-1.3.6-buildfixes.patch
+++ b/manual/CHAPTER_StateOfTheArt/mvsis-1.3.6-buildfixes.patch
diff --git a/manual/FILES_StateOfTheArt/simlib_hana.v b/manual/CHAPTER_StateOfTheArt/simlib_hana.v
index fc82f1389..fc82f1389 100644
--- a/manual/FILES_StateOfTheArt/simlib_hana.v
+++ b/manual/CHAPTER_StateOfTheArt/simlib_hana.v
diff --git a/manual/FILES_StateOfTheArt/simlib_icarus.v b/manual/CHAPTER_StateOfTheArt/simlib_icarus.v
index fdd7ef61f..fdd7ef61f 100644
--- a/manual/FILES_StateOfTheArt/simlib_icarus.v
+++ b/manual/CHAPTER_StateOfTheArt/simlib_icarus.v
diff --git a/manual/FILES_StateOfTheArt/simlib_yosys.v b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
index a2df8f648..a2df8f648 100644
--- a/manual/FILES_StateOfTheArt/simlib_yosys.v
+++ b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
diff --git a/manual/FILES_StateOfTheArt/sis-1.3.6-buildfixes.patch b/manual/CHAPTER_StateOfTheArt/sis-1.3.6-buildfixes.patch
index ad957d6b8..ad957d6b8 100644
--- a/manual/FILES_StateOfTheArt/sis-1.3.6-buildfixes.patch
+++ b/manual/CHAPTER_StateOfTheArt/sis-1.3.6-buildfixes.patch
diff --git a/manual/FILES_StateOfTheArt/synth.sh b/manual/CHAPTER_StateOfTheArt/synth.sh
index 3a7524a29..3a7524a29 100755
--- a/manual/FILES_StateOfTheArt/synth.sh
+++ b/manual/CHAPTER_StateOfTheArt/synth.sh
diff --git a/manual/FILES_StateOfTheArt/validate_tb.sh b/manual/CHAPTER_StateOfTheArt/validate_tb.sh
index b6409eb14..b6409eb14 100755
--- a/manual/FILES_StateOfTheArt/validate_tb.sh
+++ b/manual/CHAPTER_StateOfTheArt/validate_tb.sh