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Diffstat (limited to 'manual/manual.tex')
| -rw-r--r-- | manual/manual.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/manual/manual.tex b/manual/manual.tex index 84be86e5b..67982cbc8 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -17,7 +17,7 @@ % (i.e. run "sudo su" and then execute the commands in the root % shell, don't just prefix the commands with "sudo"). -% formats the text accourding the set language +% formats the text according the set language \usepackage[english]{babel} \usepackage[table,usenames]{xcolor} % generates indices with the "\index" command @@ -151,14 +151,14 @@ availability of a Free and Open Source (FOSS) synthesis tool that can be used as basis for custom tools would be helpful. In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was -developped. This document covers the design and implementation of this tool. +developed. This document covers the design and implementation of this tool. At the moment the main focus of Yosys lies on the high-level aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used by Yosys to perform advanced gate-level optimizations. An evaluation of Yosys based on real-world designs is included. It is shown that Yosys can be used as-is to synthesize such designs. The results produced -by Yosys in this tests where successflly verified using formal verification +by Yosys in this tests where successfully verified using formal verification and are comparable in quality to the results produced by a commercial synthesis tool. @@ -172,7 +172,7 @@ University of Technology \cite{BACC}. AIG & And-Inverter-Graph \\ ASIC & Application-Specific Integrated Circuit \\ AST & Abstract Syntax Tree \\ -BDD & Binary Decicion Diagram \\ +BDD & Binary Decision Diagram \\ BLIF & Berkeley Logic Interchange Format \\ EDA & Electronic Design Automation \\ EDIF & Electronic Design Interchange Format \\ |