diff options
Diffstat (limited to 'manual/CHAPTER_Verilog.tex')
| -rw-r--r-- | manual/CHAPTER_Verilog.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Verilog.tex b/manual/CHAPTER_Verilog.tex index 80f55a258..960747747 100644 --- a/manual/CHAPTER_Verilog.tex +++ b/manual/CHAPTER_Verilog.tex @@ -533,7 +533,7 @@ end This is translated by the Verilog and AST frontends into the following RTLIL code (attributes, cell parameters and wire declarations not included): -\begin{lstlisting}[numbers=left,frame=single] +\begin{lstlisting}[numbers=left,frame=single,language=rtlil] cell $logic_not $logic_not$<input>:4$2 connect \A \in1 connect \Y $logic_not$<input>:4$2_Y |