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Diffstat (limited to 'manual/CHAPTER_Techmap.tex')
| -rw-r--r-- | manual/CHAPTER_Techmap.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex index be74c3567..e5c7456c4 100644 --- a/manual/CHAPTER_Techmap.tex +++ b/manual/CHAPTER_Techmap.tex @@ -27,12 +27,12 @@ cells with the provided implementation. When no map file is provided, {\tt techmap} uses a built-in map file that maps the Yosys RTL cell types to the internal gate library used by Yosys. -The curious reader may find this map file as {\tt techlibs/common/stdcells.v} in +The curious reader may find this map file as {\tt techlibs/common/techmap.v} in the Yosys source tree. Additional features have been added to {\tt techmap} to allow for conditional mapping of cells (see {\tt help techmap} or Sec.~\ref{cmd:techmap}). This can -for example be usefull if the target architecture supports hardware multipliers for +for example be useful if the target architecture supports hardware multipliers for certain bit-widths but not for others. A usual synthesis flow would first use the {\tt techmap} pass to directly map |