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Diffstat (limited to 'manual/APPNOTE_011_Design_Investigation')
5 files changed, 32 insertions, 0 deletions
diff --git a/manual/APPNOTE_011_Design_Investigation/.gitignore b/manual/APPNOTE_011_Design_Investigation/.gitignore new file mode 100644 index 000000000..b6fb30680 --- /dev/null +++ b/manual/APPNOTE_011_Design_Investigation/.gitignore @@ -0,0 +1,4 @@ +example_00.dot +example_01.dot +example_02.dot +splice.dot diff --git a/manual/APPNOTE_011_Design_Investigation/example.v b/manual/APPNOTE_011_Design_Investigation/example.v new file mode 100644 index 000000000..ec272011c --- /dev/null +++ b/manual/APPNOTE_011_Design_Investigation/example.v @@ -0,0 +1,5 @@ +module example(input clk, a, b, c, output reg [1:0] y); +always @(posedge clk) + if (c) + y <= c ? a + b : 2'd0; +endmodule diff --git a/manual/APPNOTE_011_Design_Investigation/example.ys b/manual/APPNOTE_011_Design_Investigation/example.ys new file mode 100644 index 000000000..6c9ff7983 --- /dev/null +++ b/manual/APPNOTE_011_Design_Investigation/example.ys @@ -0,0 +1,6 @@ +read_verilog example.v +show -format dot -prefix example_00 +proc +show -format dot -prefix example_01 +opt +show -format dot -prefix example_02 diff --git a/manual/APPNOTE_011_Design_Investigation/make.sh b/manual/APPNOTE_011_Design_Investigation/make.sh new file mode 100644 index 000000000..60c6c6be3 --- /dev/null +++ b/manual/APPNOTE_011_Design_Investigation/make.sh @@ -0,0 +1,8 @@ +#!/bin/bash +../../yosys example.ys +../../yosys -p 'proc; opt; show -format dot -prefix splice' splice.v +sed -i '/^label=/ d;' example_*.dot splice.dot +dot -Tpdf -o example_00.pdf example_00.dot +dot -Tpdf -o example_01.pdf example_01.dot +dot -Tpdf -o example_02.pdf example_02.dot +dot -Tpdf -o splice.pdf splice.dot diff --git a/manual/APPNOTE_011_Design_Investigation/splice.v b/manual/APPNOTE_011_Design_Investigation/splice.v new file mode 100644 index 000000000..b6796c516 --- /dev/null +++ b/manual/APPNOTE_011_Design_Investigation/splice.v @@ -0,0 +1,9 @@ +module splice_demo(a, b, c, d, e, f, x, y); + +input [1:0] a, b, c, d, e, f; +output [1:0] x = {a[0], a[1]}; + +output [11:0] y; +assign {y[11:4], y[1:0], y[3:2]} = {a, b, -{c, d}, ~{e, f}}; + +endmodule |