diff options
Diffstat (limited to 'frontends/verilog')
-rw-r--r-- | frontends/verilog/preproc.cc | 10 | ||||
-rw-r--r-- | frontends/verilog/verilog_lexer.l | 15 | ||||
-rw-r--r-- | frontends/verilog/verilog_parser.y | 30 |
3 files changed, 42 insertions, 13 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 17f567587..883531e78 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -142,6 +142,16 @@ static std::string next_token(bool pass_newline = false) return_char(ch); } } + else if (ch == '\\') + { + while ((ch = next_char()) != 0) { + if (ch < 33 || ch > 126) { + return_char(ch); + break; + } + token += ch; + } + } else if (ch == '/') { if ((ch = next_char()) != 0) { diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 89c1aa895..958809319 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -128,6 +128,11 @@ static bool isUserType(std::string &s) %x IMPORT_DPI %x BASED_CONST +UNSIGNED_NUMBER [0-9][0-9_]* +FIXED_POINT_NUMBER_DEC [0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? +FIXED_POINT_NUMBER_NO_DEC [0-9][0-9_]*[eE][-+]?[0-9_]+ +TIME_SCALE_SUFFIX [munpf]?s + %% // Initialise comment_caller to something to avoid a "maybe undefined" // warning from GCC. @@ -297,7 +302,7 @@ static bool isUserType(std::string &s) "union" { SV_KEYWORD(TOK_UNION); } "packed" { SV_KEYWORD(TOK_PACKED); } -[0-9][0-9_]* { +{UNSIGNED_NUMBER} { yylval->string = new std::string(yytext); return TOK_CONSTVAL; } @@ -319,12 +324,12 @@ static bool isUserType(std::string &s) return TOK_BASED_CONSTVAL; } -[0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? { +{FIXED_POINT_NUMBER_DEC} { yylval->string = new std::string(yytext); return TOK_REALVAL; } -[0-9][0-9_]*[eE][-+]?[0-9_]+ { +{FIXED_POINT_NUMBER_NO_DEC} { yylval->string = new std::string(yytext); return TOK_REALVAL; } @@ -574,6 +579,10 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { return TOK_SPECIFY_AND; } +{UNSIGNED_NUMBER}{TIME_SCALE_SUFFIX} { return TOK_TIME_SCALE; } +{FIXED_POINT_NUMBER_DEC}{TIME_SCALE_SUFFIX} { return TOK_TIME_SCALE; } +{FIXED_POINT_NUMBER_NO_DEC}{TIME_SCALE_SUFFIX} { return TOK_TIME_SCALE; } + <INITIAL,BASED_CONST>"/*" { comment_caller=YY_START; BEGIN(COMMENT); } <COMMENT>. /* ignore comment body */ <COMMENT>\n /* ignore comment body */ diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8d0ba4cf6..c533b0c40 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -33,6 +33,8 @@ * */ +%require "3.0" + %{ #include <list> #include <stack> @@ -367,7 +369,7 @@ static void rewriteGenForDeclInit(AstNode *loop) %token TOK_BIT_OR_ASSIGN TOK_BIT_AND_ASSIGN TOK_BIT_XOR_ASSIGN TOK_ADD_ASSIGN %token TOK_SUB_ASSIGN TOK_DIV_ASSIGN TOK_MOD_ASSIGN TOK_MUL_ASSIGN %token TOK_SHL_ASSIGN TOK_SHR_ASSIGN TOK_SSHL_ASSIGN TOK_SSHR_ASSIGN -%token TOK_BIND +%token TOK_BIND TOK_TIME_SCALE %type <ast> range range_or_multirange non_opt_range non_opt_multirange %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list non_io_wire_type io_wire_type @@ -777,6 +779,9 @@ non_opt_delay: '#' TOK_ID { delete $2; } | '#' TOK_CONSTVAL { delete $2; } | '#' TOK_REALVAL { delete $2; } | + // our `expr` doesn't have time_scale, so we need the parenthesized variant + '#' TOK_TIME_SCALE | + '#' '(' TOK_TIME_SCALE ')' | '#' '(' mintypmax_expr ')' | '#' '(' mintypmax_expr ',' mintypmax_expr ')' | '#' '(' mintypmax_expr ',' mintypmax_expr ',' mintypmax_expr ')'; @@ -832,16 +837,10 @@ opt_wire_type_token: wire_type_token | %empty; wire_type_token: - TOK_WOR { - astbuf3->is_wor = true; - } | - TOK_WAND { - astbuf3->is_wand = true; + // nets + net_type { } | - // wires - TOK_WIRE { - } | - TOK_WIRE logic_type { + net_type logic_type { } | // regs TOK_REG { @@ -868,6 +867,15 @@ wire_type_token: astbuf3->range_right = 0; }; +net_type: + TOK_WOR { + astbuf3->is_wor = true; + } | + TOK_WAND { + astbuf3->is_wand = true; + } | + TOK_WIRE; + logic_type: TOK_LOGIC { } | @@ -2674,6 +2682,7 @@ for_initialization: AstNode *node = new AstNode(AST_ASSIGN_EQ, ident, $3); ast_stack.back()->children.push_back(node); SET_AST_NODE_LOC(node, @1, @3); + delete $1; } | non_io_wire_type range TOK_ID { frontend_verilog_yyerror("For loop variable declaration is missing initialization!"); @@ -2973,6 +2982,7 @@ rvalue: hierarchical_id '[' expr ']' '.' rvalue { $$ = new AstNode(AST_PREFIX, $3, $6); $$->str = *$1; + SET_AST_NODE_LOC($$, @1, @6); delete $1; } | hierarchical_id range { |