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-rw-r--r--frontends/verific/verific.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 231003753..c03e16eb2 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -917,6 +917,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
} else {
log("Importing module %s.\n", RTLIL::id2cstr(module->name));
}
+ import_attributes(module->attributes, nl, nl);
SetIter si;
MapIter mi, mi2;