1 files changed, 60 insertions, 24 deletions

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 009b28455..7e91c8cac 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -446,12 +446,30 @@ next_line:
                 log_assert(wire);
                 log_assert(wire->port_input);
 
-                if (index == 0)
-                    module->rename(wire, escaped_s);
+                if (index == 0) {
+                    // Cope with the fact that a CI might be identical
+                    // to a PI (necessary due to ABC); in those cases
+                    // simply connect the latter to the former
+                    RTLIL::Wire* existing = module->wire(escaped_s);
+                    if (!existing)
+                        module->rename(wire, escaped_s);
+                    else {
+                        wire->port_input = false;
+                        module->connect(wire, existing);
+                    }
+                }
                 else if (index > 0) {
-                    module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index));
-                    if (wideports)
-                        wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
+                    std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
+                    RTLIL::Wire* existing = module->wire(indexed_name);
+                    if (!existing) {
+                        module->rename(wire, indexed_name);
+                        if (wideports)
+                            wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
+                    }
+                    else {
+                        module->connect(wire, existing);
+                        wire->port_input = false;
+                    }
                 }
             }
             else if (type == "output") {
@@ -461,30 +479,48 @@ next_line:
                 log_assert(wire->port_output);
 
                 if (index == 0) {
-                    if (escaped_s.ends_with("$inout.out")) {
+                    // Cope with the fact that a CO might be identical
+                    // to a PO (necessary due to ABC); in those cases
+                    // simply connect the latter to the former
+                    RTLIL::Wire* existing = module->wire(escaped_s);
+                    if (!existing) {
+                        if (escaped_s.ends_with("$inout.out")) {
+                            wire->port_output = false;
+                            RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
+                            log_assert(in_wire);
+                            log_assert(in_wire->port_input && !in_wire->port_output);
+                            in_wire->port_output = true;
+                            module->connect(in_wire, wire);
+                        }
+                        else
+                            module->rename(wire, escaped_s);
+                    }
+                    else {
                         wire->port_output = false;
-                        RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
-                        log_assert(in_wire);
-                        log_assert(in_wire->port_input && !in_wire->port_output);
-                        in_wire->port_output = true;
-                        module->connect(in_wire, wire);
+                        module->connect(wire, existing);
                     }
-                    else
-                        module->rename(wire, escaped_s);
                 }
-                else if (index > 0)  {
-                    if (escaped_s.ends_with("$inout.out")) {
-                        wire->port_output = false;
-                        RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
-                        log_assert(in_wire);
-                        log_assert(in_wire->port_input && !in_wire->port_output);
-                        in_wire->port_output = true;
-                        module->connect(in_wire, wire);
+                else if (index > 0) {
+                    std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
+                    RTLIL::Wire* existing = module->wire(indexed_name);
+                    if (!existing) {
+                        if (escaped_s.ends_with("$inout.out")) {
+                            wire->port_output = false;
+                            RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
+                            log_assert(in_wire);
+                            log_assert(in_wire->port_input && !in_wire->port_output);
+                            in_wire->port_output = true;
+                            module->connect(in_wire, wire);
+                        }
+                        else {
+                            module->rename(wire, indexed_name);
+                            if (wideports)
+                                wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
+                        }
                     }
                     else {
-                        module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index));
-                        if (wideports)
-                            wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
+                        module->connect(wire, existing);
+                        wire->port_output = false;
                     }
                 }
             }