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Diffstat (limited to 'README')
| -rw-r--r-- | README | 18 |
1 files changed, 14 insertions, 4 deletions
@@ -88,9 +88,13 @@ some simple optimizations: yosys> proc; opt -display design netlist using 'gv' as postscript viewer: +display design netlist using the yosys svg viewer: - yosys> show -viewer gv + yosys> show + +the same thing using 'gv' as postscript viewer: + + yosys> show -format ps -viewer gv translating netlist to gate logic and perform some simple optimizations: @@ -205,6 +209,12 @@ Verilog Attributes and non-standard features temporary variable within an always block. This is mostly used internally by yosys to synthesize verilog functions and access arrays. +- The "placeholder" attribute on modules is used to mark empty stub modules + that have the same ports as the real thing but do not contain information + on the internal configuration. This modules are only used by the synthesis + passes to identify input and output ports of cells. The verilog backend + also does not output placeholder modules on default. + - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset @@ -240,8 +250,8 @@ TODOs / Open Bugs - Actually use range information on parameters - Add brief source code documentation to most passes and kernel code - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees - - Add commands 'delete' (remove objects) and 'attr' (get, set and remove attributes) - - TCL and Python interfaces to frontends, passes, backends and RTLIL + - Add 'edit' command for changing the design (delete, add, modify objects) + - Improve TCL support and add 'list' command for inspecting the design from TCL - Additional internal cell types: $pla and $lut - Support for registering designs (as collection of modules) to CellTypes - Smarter resource sharing pass (add MUXes and get rid of duplicated cells) |