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Diffstat (limited to 'README')
| -rw-r--r-- | README | 18 |
1 files changed, 10 insertions, 8 deletions
@@ -56,7 +56,7 @@ For example on Ubuntu Linux 14.04 LTS the following commands will install all prerequisites for building yosys: $ yosys_deps="build-essential clang bison flex libreadline-dev gawk - tcl-dev libffi-dev git mercurial graphviz xdot pkg-config python" + tcl-dev libffi-dev git mercurial graphviz xdot pkg-config python3" $ sudo apt-get install $yosys_deps There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well @@ -190,15 +190,13 @@ for the given cell library: clean If you do not have a liberty file but want to test this synthesis script, -you can use the file techlibs/cmos/cmos_cells.lib from the yosys sources. +you can use the file examples/cmos/cmos_cells.lib from the yosys sources. -Various more complex liberty files (for testing) can be found here: +Liberty file downloads for and information about free and open ASIC standard +cell libraries can be found here: - http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/.. - ../cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib - ../cadence/lib/ami035/signalstorm/osu035_stdcells.lib - ../cadence/lib/tsmc018/signalstorm/osu018_stdcells.lib - ../cadence/lib/ami05/signalstorm/osu05_stdcells.lib + http://www.vlsitechnology.org/html/libraries.html + http://www.vlsitechnology.org/synopsys/vsclib013.lib The command "synth" provides a good default synthesis script (see "help synth"). If possible a synthesis script should borrow from "synth". For example: @@ -367,6 +365,10 @@ Verilog Attributes and non-standard features expressions as <size>. If the expression is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 +- The system tasks $finish and $display are supported in initial blocks + in and unconditional context (only if/case statements on parameters + and constant values). The intended use for this is synthesis-time DRC. + Supported features from SystemVerilog ===================================== |