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Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 15 |
1 files changed, 15 insertions, 0 deletions
@@ -3,6 +3,18 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.9 .. Yosys 0.9-dev +-------------------------- + + * Various + - Added "write_xaiger" backend + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "synth_xilinx -abc9" (experimental) + - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) + - Added "script -scriptwire + + Yosys 0.8 .. Yosys 0.8-dev -------------------------- @@ -23,6 +35,9 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "muxcover -nopartial" - Added "muxpack" pass - Added "pmux2shiftx -norange" + - Added "synth_xilinx -nocarry" + - Added "synth_xilinx -nowidelut" + - Added "synth_ecp5 -nowidelut" - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - Fixed sign extension of unsized constants with 'bx and 'bz MSB |