diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | backends/btor/.gitignore | 1 | ||||
| -rw-r--r-- | backends/smv/.gitignore | 1 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 2 | ||||
| -rw-r--r-- | frontends/verific/verificsva.cc | 10 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 13 | ||||
| -rw-r--r-- | tests/aiger/.gitignore | 4 | ||||
| -rw-r--r-- | tests/svtypes/multirange_array.sv | 16 | ||||
| -rw-r--r-- | tests/svtypes/multirange_subarray_access.ys | 12 |
9 files changed, 53 insertions, 8 deletions
@@ -123,7 +123,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.9+3558 +YOSYS_VER := 0.9+3578 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o diff --git a/backends/btor/.gitignore b/backends/btor/.gitignore new file mode 100644 index 000000000..d23d492d7 --- /dev/null +++ b/backends/btor/.gitignore @@ -0,0 +1 @@ +/test_cells.tmp/ diff --git a/backends/smv/.gitignore b/backends/smv/.gitignore new file mode 100644 index 000000000..d23d492d7 --- /dev/null +++ b/backends/smv/.gitignore @@ -0,0 +1 @@ +/test_cells.tmp/ diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 0ba2ab6ac..153a42e19 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1523,7 +1523,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++) { - if (GetSize(children[0]->children) < i) + if (GetSize(children[0]->children) <= i) log_file_error(filename, location.first_line, "Insufficient number of array indices for %s.\n", log_id(str)); AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone(); diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 49c0c40ac..632043b6f 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1040,8 +1040,14 @@ struct VerificSvaImporter [[noreturn]] void parser_error(Instance *inst) { - parser_error(stringf("Verific SVA primitive %s (%s) is currently unsupported in this context", - inst->View()->Owner()->Name(), inst->Name()), inst->Linefile()); + std::string msg; + if (inst->Type() == PRIM_SVA_MATCH_ITEM_TRIGGER || inst->Type() == PRIM_SVA_MATCH_ITEM_ASSIGN) + { + msg = "SVA sequences with local variable assignments are currently not supported.\n"; + } + + parser_error(stringf("%sVerific SVA primitive %s (%s) is currently unsupported in this context", + msg.c_str(), inst->View()->Owner()->Name(), inst->Name()), inst->Linefile()); } dict<Net*, bool, hash_ptr_ops> check_expression_cache; diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 63f0341d9..8e5236639 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -210,14 +210,23 @@ static AstNode *checkRange(AstNode *type_node, AstNode *range_node) return range_node; } -static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode) +static void rewriteRange(AstNode *rangeNode) { - node->type = AST_MEMORY; if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) { // SV array size [n], rewrite as [n-1:0] rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)); rangeNode->children.push_back(AstNode::mkconst_int(0, false)); } +} + +static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode) +{ + node->type = AST_MEMORY; + if (rangeNode->type == AST_MULTIRANGE) { + for (auto *itr : rangeNode->children) + rewriteRange(itr); + } else + rewriteRange(rangeNode); node->children.push_back(rangeNode); } diff --git a/tests/aiger/.gitignore b/tests/aiger/.gitignore index b76bdb653..54b4a279b 100644 --- a/tests/aiger/.gitignore +++ b/tests/aiger/.gitignore @@ -1,3 +1,3 @@ /*_ref.v -/*.aag.log -/*.aig.log +/*.log +/neg.out/ diff --git a/tests/svtypes/multirange_array.sv b/tests/svtypes/multirange_array.sv new file mode 100644 index 000000000..be0d3dfc2 --- /dev/null +++ b/tests/svtypes/multirange_array.sv @@ -0,0 +1,16 @@ +// test for multirange arrays + +`define STRINGIFY(x) `"x`" +`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) + +module top; + + logic a [3]; + logic b [3][5]; + logic c [3][5][7]; + + `STATIC_ASSERT($bits(a) == 3); + `STATIC_ASSERT($bits(b) == 15); + `STATIC_ASSERT($bits(c) == 105); + +endmodule diff --git a/tests/svtypes/multirange_subarray_access.ys b/tests/svtypes/multirange_subarray_access.ys new file mode 100644 index 000000000..de57d1423 --- /dev/null +++ b/tests/svtypes/multirange_subarray_access.ys @@ -0,0 +1,12 @@ +logger -expect error "Insufficient number of array indices for a." 1 +read_verilog -sv <<EOT +module foo; +logic a [6:0][4:0][1:0]; +logic b [1:0]; + +assign a[0][0][0] = 1'b0; +assign a[0][0][1] = 1'b1; +assign b = a[0][0]; + +endmodule +EOT |