diff options
| -rw-r--r-- | CHANGELOG | 2 | ||||
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | frontends/ast/genrtlil.cc | 5 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 2 | ||||
| -rw-r--r-- | passes/memory/memory_share.cc | 4 | ||||
| -rw-r--r-- | techlibs/intel_alm/common/bram_m10k.txt | 12 | ||||
| -rw-r--r-- | tests/opt/bug3117.ys | 34 | ||||
| -rw-r--r-- | tests/simple/case_expr_extend.sv | 11 | ||||
| -rw-r--r-- | tests/simple/case_expr_query.sv | 32 |
9 files changed, 91 insertions, 13 deletions
@@ -14,6 +14,8 @@ Yosys 0.11 .. Yosys 0.12 * SystemVerilog - Support parameters using struct as a wiretype + - Fixed regression preventing the use array querying functions in case + expressions and case item expressions * New commands and options - Added "-genlib" option to "abc" pass @@ -129,7 +129,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.12+30 +YOSYS_VER := 0.12+42 GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index ed709aa33..1fe74bb72 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1087,6 +1087,11 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun } break; } + if (str == "\\$size" || str == "\\$bits" || str == "\\$high" || str == "\\$low" || str == "\\$left" || str == "\\$right") { + width_hint = 32; + sign_hint = true; + break; + } if (current_scope.count(str)) { // This width detection is needed for function calls which are diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 777f46bd7..cb47e641a 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1389,8 +1389,6 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (const_fold && type == AST_CASE) { - int width_hint; - bool sign_hint; detectSignWidth(width_hint, sign_hint); while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { } if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) { diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 9d82739aa..ceea725d8 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -416,7 +416,9 @@ struct MemoryShareWorker else this_addr.extend_u0(GetSize(last_addr)); - port1.addr = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); + SigSpec new_addr = module->Mux(NEW_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active); + + port1.addr = SigSpec({new_addr, port1.addr.extract(0, port1.wide_log2)}); port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active); std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en; diff --git a/techlibs/intel_alm/common/bram_m10k.txt b/techlibs/intel_alm/common/bram_m10k.txt index e9355fe2c..0d9a49b7d 100644 --- a/techlibs/intel_alm/common/bram_m10k.txt +++ b/techlibs/intel_alm/common/bram_m10k.txt @@ -4,18 +4,12 @@ bram MISTRAL_M10K dbits 1 @D8192x1 abits 12 @D4096x2 dbits 2 @D4096x2 - abits 11 @D2048x4 @D2048x5 - dbits 4 @D2048x4 + abits 11 @D2048x5 dbits 5 @D2048x5 - abits 10 @D1024x8 @D1024x10 - dbits 8 @D1024x8 + abits 10 @D1024x10 dbits 10 @D1024x10 - abits 9 @D512x16 @D512x20 - dbits 16 @D512x16 + abits 9 @D512x20 dbits 20 @D512x20 - abits 8 @D256x32 @D256x40 - dbits 32 @D256x32 - dbits 40 @D256x40 groups 2 ports 1 1 wrmode 1 0 diff --git a/tests/opt/bug3117.ys b/tests/opt/bug3117.ys new file mode 100644 index 000000000..177b3ab9a --- /dev/null +++ b/tests/opt/bug3117.ys @@ -0,0 +1,34 @@ +read_verilog << EOT + +module test (...); + +input [7:1] wa1; +input [7:1] wa2; +input [7:0] ra; +output [7:0] rd; +input clk; +input we1, we2; +input [15:0] wd1, wd2; + +reg [7:0] mem [0:255]; + +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we1) begin + mem[{wa1, 1'b0}] <= wd1[7:0]; + mem[{wa1, 1'b1}] <= wd1[15:8]; + end else begin + mem[{wa2, 1'b0}] <= wd2[7:0]; + mem[{wa2, 1'b1}] <= wd2[15:8]; + end +end + +endmodule + +EOT + +proc +opt +memory_share +select -assert-count 1 t:$memwr_v2 diff --git a/tests/simple/case_expr_extend.sv b/tests/simple/case_expr_extend.sv new file mode 100644 index 000000000..61bd14df1 --- /dev/null +++ b/tests/simple/case_expr_extend.sv @@ -0,0 +1,11 @@ +module top( + output logic [5:0] out +); +always_comb begin + out = '0; + case (1'b1 << 1) + 2'b10: out = '1; + default: out = '0; + endcase +end +endmodule diff --git a/tests/simple/case_expr_query.sv b/tests/simple/case_expr_query.sv new file mode 100644 index 000000000..63a0a8b7a --- /dev/null +++ b/tests/simple/case_expr_query.sv @@ -0,0 +1,32 @@ +module top( + output logic [5:0] out +); +always_comb begin + out = '0; + case ($bits (out)) 6: + case ($size (out)) 6: + case ($high (out)) 5: + case ($low (out)) 0: + case ($left (out)) 5: + case ($right(out)) 0: + case (6) $bits (out): + case (6) $size (out): + case (5) $high (out): + case (0) $low (out): + case (5) $left (out): + case (0) $right(out): + out = '1; + endcase + endcase + endcase + endcase + endcase + endcase + endcase + endcase + endcase + endcase + endcase + endcase +end +endmodule |