diff options
| -rw-r--r-- | passes/memory/memory_dff.cc | 8 | ||||
| -rw-r--r-- | tests/arch/ecp5/bug2409.ys | 24 |
2 files changed, 32 insertions, 0 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 68023fd11..4adcb462e 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -46,8 +46,15 @@ struct MemoryDffWorker { sigmap.apply(sig); + dict<SigBit, SigBit> cache; + for (auto &bit : sig) { + if (cache.count(bit)) { + bit = cache[bit]; + continue; + } + if (bit.wire == NULL) continue; @@ -103,6 +110,7 @@ struct MemoryDffWorker d = module->Mux(NEW_ID, rbit, d, cell->getPort(ID::SRST)); } + cache[bit] = d; bit = d; clk = this_clk; clk_polarity = this_clk_polarity; diff --git a/tests/arch/ecp5/bug2409.ys b/tests/arch/ecp5/bug2409.ys new file mode 100644 index 000000000..5ba9cec17 --- /dev/null +++ b/tests/arch/ecp5/bug2409.ys @@ -0,0 +1,24 @@ +read_verilog <<EOT +module t (...); + +input CLK; +input [10:0] A; +input WE; +input C; +input [7:0] DI; +output reg [7:0] DO; + +reg [7:0] mem[2047:0]; + +always @(posedge CLK) begin + if (C) + if (WE) + mem[A] <= DI; + DO <= mem[A]; +end + +endmodule +EOT + +synth_ecp5 +select -assert-count 1 t:DP16KD |