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-rw-r--r--Makefile4
-rw-r--r--frontends/verific/verific.cc2
-rw-r--r--kernel/fstdata.cc9
-rw-r--r--libs/fst/config.h3
-rw-r--r--passes/memory/memory_share.cc14
-rw-r--r--passes/opt/opt_dff.cc2
-rw-r--r--passes/sat/sim.cc98
7 files changed, 98 insertions, 34 deletions
diff --git a/Makefile b/Makefile
index 38bafc2f1..e95c5f491 100644
--- a/Makefile
+++ b/Makefile
@@ -129,7 +129,7 @@ LDFLAGS += -rdynamic
LDLIBS += -lrt
endif
-YOSYS_VER := 0.16+31
+YOSYS_VER := 0.16+41
GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
OBJS = kernel/version_$(GIT_REV).o
@@ -142,7 +142,7 @@ bumpversion:
# is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC..
-ABCREV = 00b674d
+ABCREV = 3da9357
ABCPULL = 1
ABCURL ?= https://github.com/YosysHQ/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 VERBOSE=$(Q)
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 44196a310..284d5db31 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2548,10 +2548,12 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
+ RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
#ifdef VERIFIC_VHDL_SUPPORT
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
+ RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1);
RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc
index c99bc61c3..2bec58bcf 100644
--- a/kernel/fstdata.cc
+++ b/kernel/fstdata.cc
@@ -201,10 +201,11 @@ void FstData::reconstructAllAtTimes(std::vector<fstHandle> &signal, uint64_t sta
fstReaderSetUnlimitedTimeRange(ctx);
fstReaderSetFacProcessMaskAll(ctx);
fstReaderIterBlocks2(ctx, reconstruct_clb_attimes, reconstruct_clb_varlen_attimes, this, nullptr);
- past_data = last_data;
- callback(last_time);
- if (last_time!=end_time)
- callback(end_time);
+ if (last_time!=end_time) {
+ past_data = last_data;
+ callback(last_time);
+ }
+ callback(end_time);
}
std::string FstData::valueOf(fstHandle signal)
diff --git a/libs/fst/config.h b/libs/fst/config.h
index 0598fb8c5..cd036f16a 100644
--- a/libs/fst/config.h
+++ b/libs/fst/config.h
@@ -21,6 +21,9 @@
#undef HAVE_LIBPTHREAD
#undef HAVE_FSEEKO
#endif
+#ifdef __FreeBSD__
+#undef HAVE_ALLOCA_H
+#endif
# ifndef __STDC_FORMAT_MACROS
# define __STDC_FORMAT_MACROS 1
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index ceea725d8..1ddc13f90 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -82,6 +82,11 @@ struct MemoryShareWorker
log("Consolidating read ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
bool changed = false;
+ int abits = 0;
+ for (auto &port: mem.rd_ports) {
+ if (GetSize(port.addr) > abits)
+ abits = GetSize(port.addr);
+ }
for (int i = 0; i < GetSize(mem.rd_ports); i++)
{
auto &port1 = mem.rd_ports[i];
@@ -114,6 +119,8 @@ struct MemoryShareWorker
int wide_log2 = std::max(port1.wide_log2, port2.wide_log2);
SigSpec addr1 = sigmap_xmux(port1.addr);
SigSpec addr2 = sigmap_xmux(port2.addr);
+ addr1.extend_u0(abits);
+ addr2.extend_u0(abits);
if (GetSize(addr1) <= wide_log2)
continue;
if (GetSize(addr2) <= wide_log2)
@@ -192,6 +199,11 @@ struct MemoryShareWorker
log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
bool changed = false;
+ int abits = 0;
+ for (auto &port: mem.wr_ports) {
+ if (GetSize(port.addr) > abits)
+ abits = GetSize(port.addr);
+ }
for (int i = 0; i < GetSize(mem.wr_ports); i++)
{
auto &port1 = mem.wr_ports[i];
@@ -216,6 +228,8 @@ struct MemoryShareWorker
int wide_log2 = std::max(port1.wide_log2, port2.wide_log2);
SigSpec addr1 = sigmap_xmux(port1.addr);
SigSpec addr2 = sigmap_xmux(port2.addr);
+ addr1.extend_u0(abits);
+ addr2.extend_u0(abits);
if (GetSize(addr1) <= wide_log2)
continue;
if (GetSize(addr2) <= wide_log2)
diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc
index 73d674c8d..0ad4acec2 100644
--- a/passes/opt/opt_dff.cc
+++ b/passes/opt/opt_dff.cc
@@ -554,7 +554,7 @@ struct OptDffWorker
// The D input path is effectively useless, so remove it (this will be a const-input D latch, SR latch, or a const driver).
log("Handling D = Q on %s (%s) from module %s (removing D path).\n",
log_id(cell), log_id(cell->type), log_id(module));
- ff.has_clk = ff.has_ce = false;
+ ff.has_gclk = ff.has_clk = ff.has_ce = false;
changed = true;
}
}
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index ca4aab566..5f795e94c 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -782,22 +782,21 @@ struct SimInstance
bool setInitState()
{
bool did_something = false;
+ for(auto &item : fst_handles) {
+ if (item.second==0) continue; // Ignore signals not found
+ std::string v = shared->fst->valueOf(item.second);
+ did_something |= set_state(item.first, Const::from_string(v));
+ }
for (auto &it : ff_database)
{
ff_state_t &ff = it.second;
- SigSpec qsig = it.second.data.sig_q;
- if (qsig.is_wire()) {
- IdString name = qsig.as_wire()->name;
- fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(name));
- if (id==0 && name.isPublic())
- log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
- if (id!=0) {
- Const fst_val = Const::from_string(shared->fst->valueOf(id));
- ff.past_d = fst_val;
- if (ff.data.has_aload)
- ff.past_ad = fst_val;
- did_something = set_state(qsig, fst_val);
- }
+ SigSpec dsig = it.second.data.sig_d;
+ Const value = get_state(dsig);
+ if (dsig.is_wire()) {
+ ff.past_d = value;
+ if (ff.data.has_aload)
+ ff.past_ad = value;
+ did_something |= true;
}
}
for (auto child : children)
@@ -805,6 +804,31 @@ struct SimInstance
return did_something;
}
+ void addAdditionalInputs(std::map<Wire*,fstHandle> &inputs)
+ {
+ for (auto cell : module->cells())
+ {
+ if (cell->type.in(ID($anyseq))) {
+ SigSpec sig_y = sigmap(cell->getPort(ID::Y));
+ if (sig_y.is_wire()) {
+ bool found = false;
+ for(auto &item : fst_handles) {
+ if (item.second==0) continue; // Ignore signals not found
+ if (sig_y == sigmap(item.first)) {
+ inputs[sig_y.as_wire()] = item.second;
+ found = true;
+ break;
+ }
+ }
+ if (!found)
+ log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)).c_str());
+ }
+ }
+ }
+ for (auto child : children)
+ child.second->addAdditionalInputs(inputs);
+ }
+
void setState(dict<int, std::pair<SigBit,bool>> bits, std::string values)
{
for(auto bit : bits) {
@@ -1066,6 +1090,8 @@ struct SimWorker : SimShared
}
}
+ top->addAdditionalInputs(inputs);
+
uint64_t startCount = 0;
uint64_t stopCount = 0;
if (start_time==0) {
@@ -1231,13 +1257,13 @@ struct SimWorker : SimShared
{
std::string line;
std::getline(f, line);
- if (line.size()==0 || line[0]=='#') continue;
+ if (line.size()==0 || line[0]=='#' || line[0]=='c' || line[0]=='f' || line[0]=='u') continue;
if (line[0]=='.') break;
if (state==0 && line.size()!=1) {
// old format detected, latch data
state = 2;
}
- if (state==1 && line[0]!='b' && line[0]!='c') {
+ if (state==1 && line[0]!='b' && line[0]!='j') {
// was old format but with 1 bit latch
top->setState(latches, status);
state = 3;
@@ -1313,8 +1339,10 @@ struct SimWorker : SimShared
void run_cosim_btor2_witness(Module *topmod)
{
log_assert(top == nullptr);
- if ((clock.size()+clockn.size())==0)
+ if (!multiclock && (clock.size()+clockn.size())==0)
log_error("Clock signal must be specified.\n");
+ if (multiclock && (clock.size()+clockn.size())>0)
+ log_error("For multiclock witness there should be no clock signal.\n");
std::ifstream f;
f.open(sim_filename.c_str());
if (f.fail() || GetSize(sim_filename) == 0)
@@ -1347,10 +1375,12 @@ struct SimWorker : SimShared
set_inports(clockn, State::S0);
update();
register_output_step(10*cycle+0);
- set_inports(clock, State::S0);
- set_inports(clockn, State::S1);
- update();
- register_output_step(10*cycle+5);
+ if (!multiclock) {
+ set_inports(clock, State::S0);
+ set_inports(clockn, State::S1);
+ update();
+ register_output_step(10*cycle+5);
+ }
cycle++;
prev_cycle = curr_cycle;
}
@@ -1779,6 +1809,12 @@ struct AIWWriter : public OutputWriter
log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
if (type == "input") {
aiw_inputs[variable] = SigBit(w,index-w->start_offset);
+ if (worker->clock.count(escaped_s)) {
+ clocks[variable] = true;
+ }
+ if (worker->clockn.count(escaped_s)) {
+ clocks[variable] = false;
+ }
} else if (type == "init") {
aiw_inits[variable] = SigBit(w,index-w->start_offset);
} else if (type == "latch") {
@@ -1796,8 +1832,9 @@ struct AIWWriter : public OutputWriter
std::map<int, Yosys::RTLIL::Const> current;
bool first = true;
- for(auto& d : worker->output_data)
+ for (auto iter = worker->output_data.begin(); iter != std::prev(worker->output_data.end()); ++iter)
{
+ auto& d = *iter;
for (auto &data : d.second)
{
current[data.first] = data.second;
@@ -1806,12 +1843,7 @@ struct AIWWriter : public OutputWriter
for (int i = 0;; i++)
{
if (aiw_latches.count(i)) {
- SigBit bit = aiw_latches.at(i).first;
- auto v = current[mapping[bit.wire]].bits.at(bit.offset);
- if (v == State::S1)
- aiwfile << (aiw_latches.at(i).second ? '0' : '1');
- else
- aiwfile << (aiw_latches.at(i).second ? '1' : '0');
+ aiwfile << '0';
continue;
}
aiwfile << '\n';
@@ -1820,6 +1852,17 @@ struct AIWWriter : public OutputWriter
first = false;
}
+ bool skip = false;
+ for (auto it : clocks)
+ {
+ auto val = it.second ? State::S1 : State::S0;
+ SigBit bit = aiw_inputs.at(it.first);
+ auto v = current[mapping[bit.wire]].bits.at(bit.offset);
+ if (v == val)
+ skip = true;
+ }
+ if (skip)
+ continue;
for (int i = 0;; i++)
{
if (aiw_inputs.count(i)) {
@@ -1849,6 +1892,7 @@ struct AIWWriter : public OutputWriter
std::ofstream aiwfile;
dict<int, std::pair<SigBit, bool>> aiw_latches;
dict<int, SigBit> aiw_inputs, aiw_inits;
+ dict<int, bool> clocks;
std::map<Wire*,int> mapping;
};
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-27 04:55:11 +0000