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-rw-r--r--CHANGELOG1
-rw-r--r--backends/aiger/xaiger.cc10
-rw-r--r--passes/techmap/abc9.cc74
-rw-r--r--techlibs/ecp5/abc_5g.box5
-rw-r--r--techlibs/ecp5/cells_sim.v2
-rw-r--r--techlibs/xilinx/abc_xc7.box5
-rw-r--r--techlibs/xilinx/cells_sim.v6
7 files changed, 56 insertions, 47 deletions
diff --git a/CHANGELOG b/CHANGELOG
index abfbb7f79..82576e842 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -22,6 +22,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "muxcover -dmux=<cost>"
- Added "muxcover -nopartial"
- Added "muxpack" pass
+ - Added "write_xaiger" backend
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 7cfe8272c..92df899c2 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -293,10 +293,12 @@ struct XAigerWriter
#if 0
unsigned i = 0;
for (auto &it : toposort.loops) {
- log(" loop %d", i++);
- for (auto cell : it)
- log(" %s", log_id(cell));
- log("\n");
+ log(" loop %d\n", i++);
+ for (auto cell_name : it) {
+ auto cell = module->cell(cell_name);
+ log_assert(cell);
+ log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
+ }
}
#endif
log_assert(no_loops);
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 0312e3e1f..dbdd775f8 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -80,6 +80,8 @@ void handle_loops(RTLIL::Design *design)
{
Pass::call(design, "scc -set_attr abc_scc_id {}");
+ dict<IdString, vector<IdString>> module_break;
+
// For every unique SCC found, (arbitrarily) find the first
// cell in the component, and select (and mark) all its output
// wires
@@ -113,43 +115,45 @@ void handle_loops(RTLIL::Design *design)
}
cell->attributes.erase(it);
}
- RTLIL::Module* box_module = design->module(cell->type);
- if (box_module) {
- auto jt = box_module->attributes.find("\\abc_scc_break");
- if (jt != box_module->attributes.end()) {
- auto it = cell->connections_.find(RTLIL::escape_id(jt->second.decode_string()));
- if (it == cell->connections_.end())
- log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", jt->second.decode_string().c_str(), log_id(box_module));
- log_assert(it != cell->connections_.end());
- RTLIL::SigSpec sig;
- for (auto b : it->second) {
- Wire *w = b.wire;
- if (!w) continue;
- if (w->port_output) {
- log_assert(w->get_bool_attribute("\\abc_scc_break"));
- w = module->wire(stringf("%s.abci", w->name.c_str()));
- log_assert(w);
- log_assert(b.offset < GetSize(w));
- log_assert(w->port_input);
- }
- else {
- log_assert(!w->port_output);
- w->port_output = true;
- w->set_bool_attribute("\\abc_scc_break");
- w = module->wire(stringf("%s.abci", w->name.c_str()));
- if (!w) {
- w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
- w->port_input = true;
- }
- else {
- log_assert(w->port_input);
- log_assert(b.offset < GetSize(w));
- }
- }
- sig.append(RTLIL::SigBit(w, b.offset));
+
+ auto jt = module_break.find(cell->type);
+ if (jt == module_break.end()) {
+ std::vector<IdString> ports;
+ if (!yosys_celltypes.cell_known(cell->type)) {
+ RTLIL::Module* box_module = design->module(cell->type);
+ log_assert(box_module);
+ auto ports_csv = box_module->attributes.at("\\abc_scc_break", RTLIL::Const::from_string("")).decode_string();
+ for (const auto &port_name : split_tokens(ports_csv, ",")) {
+ auto port_id = RTLIL::escape_id(port_name);
+ auto kt = cell->connections_.find(port_id);
+ if (kt == cell->connections_.end())
+ log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", port_name.c_str(), log_id(box_module));
+ ports.push_back(port_id);
+ }
+ }
+ jt = module_break.insert(std::make_pair(cell->type, std::move(ports))).first;
+ }
+
+ for (auto port_name : jt->second) {
+ RTLIL::SigSpec sig;
+ auto &rhs = cell->connections_.at(port_name);
+ for (auto b : rhs) {
+ Wire *w = b.wire;
+ if (!w) continue;
+ w->port_output = true;
+ w->set_bool_attribute("\\abc_scc_break");
+ w = module->wire(stringf("%s.abci", w->name.c_str()));
+ if (!w) {
+ w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
+ w->port_input = true;
+ }
+ else {
+ log_assert(b.offset < GetSize(w));
+ log_assert(w->port_input);
}
- it->second = sig;
+ sig.append(RTLIL::SigBit(w, b.offset));
}
+ rhs = sig;
}
}
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index 15e26b5d5..5309aca87 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -4,8 +4,9 @@
# Box 1 : CCU2C (2xCARRY + 2xLUT4)
# Outputs: S0, S1, COUT
# (NB: carry chain input/output must be last
-# input/output and have been moved there
-# overriding the alphabetical ordering)
+# input/output and bus has been moved
+# there overriding the otherwise
+# alphabetical ordering)
# name ID w/b ins outs
CCU2C 1 1 9 3
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 45515d582..08ae0a112 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule
// ---------------------------------------
-(* abc_box_id=2, abc_scc_break="DI" *)
+(* abc_box_id=2, abc_scc_break="DI,WRE" *)
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index b1c24ed24..7fe8a7236 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -23,8 +23,9 @@ MUXF78 3 1 6 1
# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
# (NB: carry chain input/output must be last
-# input/output and have been moved there
-# overriding the alphabetical ordering)
+# input/output and the entire bus has been
+# moved there overriding the otherwise
+# alphabetical ordering)
CARRY4 4 1 10 8
482 - - - - 223 - - - 222
598 407 - - - 400 205 - - 334
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 354e4edbf..4a1e334d6 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -289,7 +289,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
-(* abc_box_id = 5, abc_scc_break="D" *)
+(* abc_box_id = 5, abc_scc_break="D,WE" *)
module RAM32X1D (
output DPO, SPO,
input D, WCLK, WE,
@@ -307,7 +307,7 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
-(* abc_box_id = 6, abc_scc_break="D" *)
+(* abc_box_id = 6, abc_scc_break="D,WE" *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
@@ -325,7 +325,7 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
-(* abc_box_id = 7, abc_scc_break="D" *)
+(* abc_box_id = 7, abc_scc_break="D,WE" *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-23 13:06:13 +0000