aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Makefile6
-rw-r--r--backends/blif/blif.cc110
-rw-r--r--backends/firrtl/firrtl.cc352
-rw-r--r--kernel/driver.cc2
-rw-r--r--kernel/yosys.cc72
-rw-r--r--kernel/yosys.h3
-rw-r--r--passes/techmap/abc.cc18
-rw-r--r--passes/techmap/abc9_exe.cc13
-rw-r--r--techlibs/gowin/cells_sim.v45
-rw-r--r--techlibs/intel/common/m9k_bb.v2
-rw-r--r--techlibs/nexus/Makefile.inc1
-rw-r--r--techlibs/nexus/cells_sim.v564
-rw-r--r--techlibs/nexus/cells_xtra.py18
-rw-r--r--techlibs/nexus/cells_xtra.v241
-rw-r--r--techlibs/nexus/dsp_map.v79
-rw-r--r--techlibs/nexus/synth_nexus.cc38
-rw-r--r--tests/arch/nexus/mul.ys46
-rw-r--r--tests/arch/nexus/run-test.sh22
18 files changed, 1190 insertions, 442 deletions
diff --git a/Makefile b/Makefile
index a83b21b26..01060dedf 100644
--- a/Makefile
+++ b/Makefile
@@ -123,7 +123,7 @@ LDFLAGS += -rdynamic
LDLIBS += -lrt
endif
-YOSYS_VER := 0.9+3667
+YOSYS_VER := 0.9+3686
GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
OBJS = kernel/version_$(GIT_REV).o
@@ -661,6 +661,10 @@ ifeq ($(LINK_ABC),1)
OBJS += $(PROGRAM_PREFIX)yosys-libabc.a
endif
+# prevent the CXXFLAGS set by this Makefile from reaching abc/Makefile,
+# especially the -MD flag which will break the build when CXX is clang
+unexport CXXFLAGS
+
top-all: $(TARGETS) $(EXTRA_TARGETS)
@echo ""
@echo " Build successful."
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 780a16320..088819042 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -86,20 +86,18 @@ struct BlifDumper
}
}
- vector<shared_str> cstr_buf;
pool<SigBit> cstr_bits_seen;
- const char *cstr(RTLIL::IdString id)
+ const std::string str(RTLIL::IdString id)
{
std::string str = RTLIL::unescape_id(id);
for (size_t i = 0; i < str.size(); i++)
if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
str[i] = '?';
- cstr_buf.push_back(str);
- return cstr_buf.back().c_str();
+ return str;
}
- const char *cstr(RTLIL::SigBit sig)
+ const std::string str(RTLIL::SigBit sig)
{
cstr_bits_seen.insert(sig);
@@ -117,11 +115,10 @@ struct BlifDumper
if (sig.wire->width != 1)
str += stringf("[%d]", sig.wire->upto ? sig.wire->start_offset+sig.wire->width-sig.offset-1 : sig.wire->start_offset+sig.offset);
- cstr_buf.push_back(str);
- return cstr_buf.back().c_str();
+ return str;
}
- const char *cstr_init(RTLIL::SigBit sig)
+ const std::string str_init(RTLIL::SigBit sig)
{
sigmap.apply(sig);
@@ -130,8 +127,7 @@ struct BlifDumper
string str = stringf(" %d", init_bits.at(sig));
- cstr_buf.push_back(str);
- return cstr_buf.back().c_str();
+ return str;
}
const char *subckt_or_gate(std::string cell_type)
@@ -168,7 +164,7 @@ struct BlifDumper
void dump()
{
f << stringf("\n");
- f << stringf(".model %s\n", cstr(module->name));
+ f << stringf(".model %s\n", str(module->name).c_str());
std::map<int, RTLIL::Wire*> inputs, outputs;
@@ -183,7 +179,7 @@ struct BlifDumper
for (auto &it : inputs) {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++)
- f << stringf(" %s", cstr(RTLIL::SigSpec(wire, i)));
+ f << stringf(" %s", str(RTLIL::SigSpec(wire, i)).c_str());
}
f << stringf("\n");
@@ -191,7 +187,7 @@ struct BlifDumper
for (auto &it : outputs) {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++)
- f << stringf(" %s", cstr(RTLIL::SigSpec(wire, i)));
+ f << stringf(" %s", str(RTLIL::SigSpec(wire, i)).c_str());
}
f << stringf("\n");
@@ -233,131 +229,131 @@ struct BlifDumper
if (config->unbuf_types.count(cell->type)) {
auto portnames = config->unbuf_types.at(cell->type);
f << stringf(".names %s %s\n1 1\n",
- cstr(cell->getPort(portnames.first)), cstr(cell->getPort(portnames.second)));
+ str(cell->getPort(portnames.first)).c_str(), str(cell->getPort(portnames.second)).c_str());
continue;
}
if (!config->icells_mode && cell->type == ID($_NOT_)) {
f << stringf(".names %s %s\n0 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AND_)) {
f << stringf(".names %s %s %s\n11 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OR_)) {
f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_XOR_)) {
f << stringf(".names %s %s %s\n10 1\n01 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NAND_)) {
f << stringf(".names %s %s %s\n0- 1\n-0 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NOR_)) {
f << stringf(".names %s %s %s\n00 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_XNOR_)) {
f << stringf(".names %s %s %s\n11 1\n00 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_ANDNOT_)) {
f << stringf(".names %s %s %s\n10 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_ORNOT_)) {
f << stringf(".names %s %s %s\n1- 1\n-0 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AOI3_)) {
f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OAI3_)) {
f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AOI4_)) {
f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
- cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
+ str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OAI4_)) {
f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
- cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
+ str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_MUX_)) {
f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
- cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
+ str(cell->getPort(ID::S)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NMUX_)) {
f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
- cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y)));
+ str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
+ str(cell->getPort(ID::S)).c_str(), str(cell->getPort(ID::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_FF_)) {
- f << stringf(".latch %s %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
- cstr_init(cell->getPort(ID::Q)));
+ f << stringf(".latch %s %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(),
+ str_init(cell->getPort(ID::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DFF_N_)) {
- f << stringf(".latch %s %s fe %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
- cstr(cell->getPort(ID::C)), cstr_init(cell->getPort(ID::Q)));
+ f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(),
+ str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DFF_P_)) {
- f << stringf(".latch %s %s re %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
- cstr(cell->getPort(ID::C)), cstr_init(cell->getPort(ID::Q)));
+ f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(),
+ str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) {
- f << stringf(".latch %s %s al %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
- cstr(cell->getPort(ID::E)), cstr_init(cell->getPort(ID::Q)));
+ f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(),
+ str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) {
- f << stringf(".latch %s %s ah %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
- cstr(cell->getPort(ID::E)), cstr_init(cell->getPort(ID::Q)));
+ f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(),
+ str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
goto internal_cell;
}
@@ -367,10 +363,10 @@ struct BlifDumper
auto width = cell->parameters.at(ID::WIDTH).as_int();
log_assert(inputs.size() == width);
for (int i = width-1; i >= 0; i--)
- f << stringf(" %s", cstr(inputs.extract(i, 1)));
+ f << stringf(" %s", str(inputs.extract(i, 1)).c_str());
auto &output = cell->getPort(ID::Y);
log_assert(output.size() == 1);
- f << stringf(" %s", cstr(output));
+ f << stringf(" %s", str(output).c_str());
f << stringf("\n");
RTLIL::SigSpec mask = cell->parameters.at(ID::LUT);
for (int i = 0; i < (1 << width); i++)
@@ -393,10 +389,10 @@ struct BlifDumper
table.push_back(State::S0);
log_assert(inputs.size() == width);
for (int i = 0; i < width; i++)
- f << stringf(" %s", cstr(inputs.extract(i, 1)));
+ f << stringf(" %s", str(inputs.extract(i, 1)).c_str());
auto &output = cell->getPort(ID::Y);
log_assert(output.size() == 1);
- f << stringf(" %s", cstr(output));
+ f << stringf(" %s", str(output).c_str());
f << stringf("\n");
for (int i = 0; i < depth; i++) {
for (int j = 0; j < width; j++) {
@@ -411,11 +407,11 @@ struct BlifDumper
goto internal_cell;
}
- f << stringf(".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type));
+ f << stringf(".%s %s", subckt_or_gate(cell->type.str()), str(cell->type).c_str());
for (auto &conn : cell->connections())
{
if (conn.second.size() == 1) {
- f << stringf(" %s=%s", cstr(conn.first), cstr(conn.second[0]));
+ f << stringf(" %s=%s", str(conn.first).c_str(), str(conn.second[0]).c_str());
continue;
}
@@ -424,20 +420,20 @@ struct BlifDumper
if (w == nullptr) {
for (int i = 0; i < GetSize(conn.second); i++)
- f << stringf(" %s[%d]=%s", cstr(conn.first), i, cstr(conn.second[i]));
+ f << stringf(" %s[%d]=%s", str(conn.first).c_str(), i, str(conn.second[i]).c_str());
} else {
for (int i = 0; i < std::min(GetSize(conn.second), GetSize(w)); i++) {
SigBit sig(w, i);
- f << stringf(" %s[%d]=%s", cstr(conn.first), sig.wire->upto ?
+ f << stringf(" %s[%d]=%s", str(conn.first).c_str(), sig.wire->upto ?
sig.wire->start_offset+sig.wire->width-sig.offset-1 :
- sig.wire->start_offset+sig.offset, cstr(conn.second[i]));
+ sig.wire->start_offset+sig.offset, str(conn.second[i]).c_str());
}
}
}
f << stringf("\n");
if (config->cname_mode)
- f << stringf(".cname %s\n", cstr(cell->name));
+ f << stringf(".cname %s\n", str(cell->name).c_str());
if (config->attr_mode)
dump_params(".attr", cell->attributes);
if (config->param_mode)
@@ -446,7 +442,7 @@ struct BlifDumper
if (0) {
internal_cell:
if (config->iname_mode)
- f << stringf(".cname %s\n", cstr(cell->name));
+ f << stringf(".cname %s\n", str(cell->name).c_str());
if (config->iattr_mode)
dump_params(".attr", cell->attributes);
}
@@ -462,12 +458,12 @@ struct BlifDumper
continue;
if (config->conn_mode)
- f << stringf(".conn %s %s\n", cstr(rhs_bit), cstr(lhs_bit));
+ f << stringf(".conn %s %s\n", str(rhs_bit).c_str(), str(lhs_bit).c_str());
else if (!config->buf_type.empty())
f << stringf(".%s %s %s=%s %s=%s\n", subckt_or_gate(config->buf_type), config->buf_type.c_str(),
- config->buf_in.c_str(), cstr(rhs_bit), config->buf_out.c_str(), cstr(lhs_bit));
+ config->buf_in.c_str(), str(rhs_bit).c_str(), config->buf_out.c_str(), str(lhs_bit).c_str());
else
- f << stringf(".names %s %s\n1 1\n", cstr(rhs_bit), cstr(lhs_bit));
+ f << stringf(".names %s %s\n1 1\n", str(rhs_bit).c_str(), str(lhs_bit).c_str());
}
f << stringf(".end\n");
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 9739a7a9f..44c3397da 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -102,6 +102,260 @@ const char *make_id(IdString id)
return namecache.at(id).c_str();
}
+std::string dump_const_string(const RTLIL::Const &data)
+{
+ std::string res_str;
+
+ std::string str = data.decode_string();
+ for (size_t i = 0; i < str.size(); i++)
+ {
+ if (str[i] == '\n')
+ res_str += "\\n";
+ else if (str[i] == '\t')
+ res_str += "\\t";
+ else if (str[i] < 32)
+ res_str += stringf("\\%03o", str[i]);
+ else if (str[i] == '"')
+ res_str += "\\\"";
+ else if (str[i] == '\\')
+ res_str += "\\\\";
+ else
+ res_str += str[i];
+ }
+
+ return res_str;
+}
+
+std::string dump_const(const RTLIL::Const &data)
+{
+ std::string res_str;
+
+ // // For debugging purposes to find out how Yosys encodes flags.
+ // res_str += stringf("flags_%x --> ", data.flags);
+
+ // Real-valued parameter.
+ if (data.flags & RTLIL::CONST_FLAG_REAL)
+ {
+ // Yosys stores real values as strings, so we call the string dumping code.
+ res_str += dump_const_string(data);
+ }
+ // String parameter.
+ else if (data.flags & RTLIL::CONST_FLAG_STRING)
+ {
+ res_str += "\"";
+ res_str += dump_const_string(data);
+ res_str += "\"";
+ }
+ // Numeric (non-real) parameter.
+ else
+ {
+ int width = data.bits.size();
+
+ // If a standard 32-bit int, then emit standard int value like "56" or
+ // "-56". Firrtl supports negative-valued int literals.
+ //
+ // SignedInt
+ // : ( '+' | '-' ) PosInt
+ // ;
+ if (width <= 32)
+ {
+ int32_t int_val = 0;
+
+ for (int i = 0; i < width; i++)
+ {
+ switch (data.bits[i])
+ {
+ case State::S0: break;
+ case State::S1: int_val |= (1 << i); break;
+ default:
+ log_error("Unexpected int value\n");
+ break;
+ }
+ }
+
+ res_str += stringf("%d", int_val);
+ }
+ else
+ {
+ // If value is larger than 32 bits, then emit a binary representation of
+ // the number as integers are not large enough to contain the result.
+ // There is a caveat to this approach though:
+ //
+ // Note that parameter may be defined as having a fixed width as follows:
+ //
+ // parameter signed [26:0] test_signed;
+ // parameter [26:0] test_unsigned;
+ // parameter signed [40:0] test_signed_large;
+ //
+ // However, if you assign a value on the RHS without specifying the
+ // precision, then yosys considers the value you used as an int and
+ // assigns it a width of 32 bits regardless of the type of the parameter.
+ //
+ // defparam <inst_name> .test_signed = 49; (width = 32, though should be 27 based on definition)
+ // defparam <inst_name> .test_unsigned = 40'd35; (width = 40, though should be 27 based on definition)
+ // defparam <inst_name> .test_signed_large = 40'd12; (width = 40)
+ //
+ // We therefore may lose the precision of the original verilog literal if
+ // it was written without its bitwidth specifier.
+
+ // Emit binary prefix for string.
+ res_str += "\"b";
+
+ // Emit bits.
+ for (int i = width - 1; i >= 0; i--)
+ {
+ log_assert(i < width);
+ switch (data.bits[i])
+ {
+ case State::S0: res_str += "0"; break;
+ case State::S1: res_str += "1"; break;
+ case State::Sx: res_str += "x"; break;
+ case State::Sz: res_str += "z"; break;
+ case State::Sa: res_str += "-"; break;
+ case State::Sm: res_str += "m"; break;
+ }
+ }
+
+ res_str += "\"";
+ }
+ }
+
+ return res_str;
+}
+
+std::string extmodule_name(RTLIL::Cell *cell, RTLIL::Module *mod_instance)
+{
+ // Since we are creating a custom extmodule for every cell that instantiates
+ // this blackbox, we need to create a custom name for it. We just use the
+ // name of the blackbox itself followed by the name of the cell.
+ const std::string cell_name = std::string(make_id(cell->name));
+ const std::string blackbox_name = std::string(make_id(mod_instance->name));
+ const std::string extmodule_name = blackbox_name + "_" + cell_name;
+ return extmodule_name;
+}
+
+/**
+ * Emits a parameterized extmodule. Instance parameters are obtained from
+ * ''cell'' as it represents the instantiation of the blackbox defined by
+ * ''mod_instance'' and therefore contains all its instance parameters.
+ */
+void emit_extmodule(RTLIL::Cell *cell, RTLIL::Module *mod_instance, std::ostream &f)
+{
+ const std::string indent = " ";
+
+ const std::string blackbox_name = std::string(make_id(mod_instance->name));
+ const std::string exported_name = extmodule_name(cell, mod_instance);
+
+ // We use the cell's fileinfo for this extmodule as its parameters come from
+ // the cell and not from the module itself (the module contains default
+ // parameters, not the instance-specific ones we're using to emit the
+ // extmodule).
+ const std::string extmoduleFileinfo = getFileinfo(cell);
+
+ // Emit extmodule header.
+ f << stringf(" extmodule %s: %s\n", exported_name.c_str(), extmoduleFileinfo.c_str());
+
+ // Emit extmodule ports.
+ for (auto wire : mod_instance->wires())
+ {
+ const auto wireName = make_id(wire->name);
+ const std::string wireFileinfo = getFileinfo(wire);
+
+ if (wire->port_input && wire->port_output)
+ {
+ log_error("Module port %s.%s is inout!\n", log_id(mod_instance), log_id(wire));
+ }
+
+ const std::string portDecl = stringf("%s%s %s: UInt<%d> %s\n",
+ indent.c_str(),
+ wire->port_input ? "input" : "output",
+ wireName,
+ wire->width,
+ wireFileinfo.c_str()
+ );
+
+ f << portDecl;
+ }
+
+ // Emit extmodule "defname" field. This is the name of the verilog blackbox
+ // that is used when verilog is emitted, so we use the name of mod_instance
+ // here.
+ f << stringf("%sdefname = %s\n", indent.c_str(), blackbox_name.c_str());
+
+ // Emit extmodule generic parameters.
+ for (const auto &p : cell->parameters)
+ {
+ const RTLIL::IdString p_id = p.first;
+ const RTLIL::Const p_value = p.second;
+
+ std::string param_name(p_id.c_str());
+ const std::string param_value = dump_const(p_value);
+
+ // Remove backslashes from parameters as these come from the internal RTLIL
+ // naming scheme, but should not exist in the emitted firrtl blackboxes.
+ // When firrtl is converted to verilog and given to downstream synthesis
+ // tools, these tools expect to find blackbox names and parameters as they
+ // were originally defined, i.e. without the extra RTLIL naming conventions.
+ param_name.erase(
+ std::remove(param_name.begin(), param_name.end(), '\\'),
+ param_name.end()
+ );
+
+ f << stringf("%sparameter %s = %s\n", indent.c_str(), param_name.c_str(), param_value.c_str());
+ }
+
+ f << "\n";
+}
+
+/**
+ * Emits extmodules for every instantiated blackbox in the design.
+ *
+ * RTLIL stores instance parameters at the cell's instantiation location.
+ * However, firrtl does not support module parameterization (everything is
+ * already elaborated). Firrtl instead supports external modules (extmodule),
+ * i.e. blackboxes that are defined by verilog and which have no body in
+ * firrtl itself other than the declaration of the blackboxes ports and
+ * parameters.
+ *
+ * Furthermore, firrtl does not support parameterization (even of extmodules)
+ * at a module's instantiation location and users must instead declare
+ * different extmodules with different instance parameters in the extmodule
+ * definition itself.
+ *
+ * This function goes through the design to identify all RTLIL blackboxes
+ * and emit parameterized extmodules with a unique name for each of them. The
+ * name that's given to the extmodule is
+ *
+ * <blackbox_name>_<instance_name>
+ *
+ * Beware that it is therefore necessary for users to replace "parameterized"
+ * instances in the RTLIL sense with these custom extmodules for the firrtl to
+ * be valid.
+ */
+void emit_elaborated_extmodules(RTLIL::Design *design, std::ostream &f)
+{
+ for (auto module : design->modules())
+ {
+ for (auto cell : module->cells())
+ {
+ // Is this cell a module instance?
+ bool cellIsModuleInstance = cell->type[0] != '$';
+
+ if (cellIsModuleInstance)
+ {
+ // Find the module corresponding to this instance.
+ auto modInstance = design->module(cell->type);
+ bool modIsBlackbox = modInstance->get_blackbox_attribute();
+
+ if (modIsBlackbox)
+ {
+ emit_extmodule(cell, modInstance, f);
+ }
+ }
+ }
+ }
+}
+
struct FirrtlWorker
{
Module *module;
@@ -328,8 +582,16 @@ struct FirrtlWorker
log_warning("No instance for %s.%s\n", cell_type.c_str(), cell_name.c_str());
return;
}
+
+ // If the instance is that of a blackbox, use the modified extmodule name
+ // that contains per-instance parameterizations. These instances were
+ // emitted earlier in the firrtl backend.
+ const std::string instanceName = instModule->get_blackbox_attribute() ?
+ extmodule_name(cell, instModule) :
+ instanceOf;
+
std::string cellFileinfo = getFileinfo(cell);
- wire_exprs.push_back(stringf("%s" "inst %s%s of %s %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), instanceOf.c_str(), cellFileinfo.c_str()));
+ wire_exprs.push_back(stringf("%s" "inst %s%s of %s %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), instanceName.c_str(), cellFileinfo.c_str()));
for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
if (it->second.size() > 0) {
@@ -392,33 +654,6 @@ struct FirrtlWorker
return result;
}
- void emit_extmodule()
- {
- std::string moduleFileinfo = getFileinfo(module);
- f << stringf(" extmodule %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
- vector<std::string> port_decls;
-
- for (auto wire : module->wires())
- {
- const auto wireName = make_id(wire->name);
- std::string wireFileinfo = getFileinfo(wire);
-
- if (wire->port_input && wire->port_output)
- {
- log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
- }
- port_decls.push_back(stringf(" %s %s: UInt<%d> %s\n", wire->port_input ? "input" : "output",
- wireName, wire->width, wireFileinfo.c_str()));
- }
-
- for (auto &str : port_decls)
- {
- f << str;
- }
-
- f << stringf("\n");
- }
-
void emit_module()
{
std::string moduleFileinfo = getFileinfo(module);
@@ -440,12 +675,12 @@ struct FirrtlWorker
{
if (wire->port_input && wire->port_output)
log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
- port_decls.push_back(stringf(" %s %s: UInt<%d> %s\n", wire->port_input ? "input" : "output",
+ port_decls.push_back(stringf("%s%s %s: UInt<%d> %s\n", indent.c_str(), wire->port_input ? "input" : "output",
wireName, wire->width, wireFileinfo.c_str()));
}
else
{
- wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", wireName, wire->width, wireFileinfo.c_str()));
+ wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent.c_str(), wireName, wire->width, wireFileinfo.c_str()));
}
}
@@ -476,7 +711,7 @@ struct FirrtlWorker
if (cell->type.in(ID($not), ID($logic_not), ID($_NOT_), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
{
string a_expr = make_expr(cell->getPort(ID::A));
- wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
+ wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent.c_str(), y_id.c_str(), y_width, cellFileinfo.c_str()));
if (a_signed) {
a_expr = "asSInt(" + a_expr + ")";
@@ -516,7 +751,7 @@ struct FirrtlWorker
if ((firrtl_is_signed && !always_uint))
expr = stringf("asUInt(%s)", expr.c_str());
- cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
+ cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent.c_str(), y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
@@ -528,7 +763,7 @@ struct FirrtlWorker
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
std::string cellFileinfo = getFileinfo(cell);
- wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
+ wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent.c_str(), y_id.c_str(), y_width, cellFileinfo.c_str()));
if (a_signed) {
a_expr = "asSInt(" + a_expr + ")";
@@ -746,7 +981,7 @@ struct FirrtlWorker
if ((firrtl_is_signed && !always_uint))
expr = stringf("asUInt(%s)", expr.c_str());
- cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
+ cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent.c_str(), y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
@@ -759,11 +994,11 @@ struct FirrtlWorker
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
string s_expr = make_expr(cell->getPort(ID::S));
- wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), width, cellFileinfo.c_str()));
+ wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent.c_str(), y_id.c_str(), width, cellFileinfo.c_str()));
string expr = stringf("mux(%s, %s, %s)", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());
- cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
+ cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent.c_str(), y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
@@ -902,9 +1137,9 @@ struct FirrtlWorker
string expr = make_expr(cell->getPort(ID::D));
string clk_expr = "asClock(" + make_expr(cell->getPort(ID::CLK)) + ")";
- wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s %s\n", y_id.c_str(), width, clk_expr.c_str(), cellFileinfo.c_str()));
+ wire_decls.push_back(stringf("%sreg %s: UInt<%d>, %s %s\n", indent.c_str(), y_id.c_str(), width, clk_expr.c_str(), cellFileinfo.c_str()));
- cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
+ cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent.c_str(), y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
register_reverse_wire_map(y_id, cell->getPort(ID::Q));
continue;
@@ -923,7 +1158,7 @@ struct FirrtlWorker
string a_expr = make_expr(cell->getPort(ID::A));
// Get the initial bit selector
string b_expr = make_expr(cell->getPort(ID::B));
- wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
+ wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent.c_str(), y_id.c_str(), y_width));
if (cell->getParam(ID::B_SIGNED).as_bool()) {
// Use validif to constrain the selection (test the sign bit)
@@ -933,7 +1168,7 @@ struct FirrtlWorker
}
string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str());
- cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
+ cell_exprs.push_back(stringf("%s%s <= %s\n", indent.c_str(), y_id.c_str(), expr.c_str()));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
@@ -945,7 +1180,7 @@ struct FirrtlWorker
string b_expr = make_expr(cell->getPort(ID::B));
auto b_string = b_expr.c_str();
string expr;
- wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
+ wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent.c_str(), y_id.c_str(), y_width));
if (cell->getParam(ID::B_SIGNED).as_bool()) {
// We generate a left or right shift based on the sign of b.
@@ -959,7 +1194,7 @@ struct FirrtlWorker
} else {
expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
}
- cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
+ cell_exprs.push_back(stringf("%s%s <= %s\n", indent.c_str(), y_id.c_str(), expr.c_str()));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
@@ -972,8 +1207,8 @@ struct FirrtlWorker
if (a_width < y_width) {
a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
}
- wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
- cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), a_expr.c_str()));
+ wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent.c_str(), y_id.c_str(), y_width));
+ cell_exprs.push_back(stringf("%s%s <= %s\n", indent.c_str(), y_id.c_str(), a_expr.c_str()));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
@@ -986,8 +1221,8 @@ struct FirrtlWorker
int y_width = GetSize(conn.first);
string expr = make_expr(conn.second);
- wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
- cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
+ wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent.c_str(), y_id.c_str(), y_width));
+ cell_exprs.push_back(stringf("%s%s <= %s\n", indent.c_str(), y_id.c_str(), expr.c_str()));
register_reverse_wire_map(y_id, conn.first);
}
@@ -1053,13 +1288,13 @@ struct FirrtlWorker
if (is_valid) {
if (make_unconn_id) {
- wire_decls.push_back(stringf(" wire %s: UInt<1> %s\n", unconn_id.c_str(), wireFileinfo.c_str()));
+ wire_decls.push_back(stringf("%swire %s: UInt<1> %s\n", indent.c_str(), unconn_id.c_str(), wireFileinfo.c_str()));
// `invalid` is a firrtl construction for simulation so we will not
// tag it with a @[fileinfo] tag as it doesn't directly correspond to
// a specific line of verilog code.
- wire_decls.push_back(stringf(" %s is invalid\n", unconn_id.c_str()));
+ wire_decls.push_back(stringf("%s%s is invalid\n", indent.c_str(), unconn_id.c_str()));
}
- wire_exprs.push_back(stringf(" %s <= %s %s\n", make_id(wire->name), expr.c_str(), wireFileinfo.c_str()));
+ wire_exprs.push_back(stringf("%s%s <= %s %s\n", indent.c_str(), make_id(wire->name), expr.c_str(), wireFileinfo.c_str()));
} else {
if (make_unconn_id) {
unconn_id.clear();
@@ -1067,7 +1302,7 @@ struct FirrtlWorker
// `invalid` is a firrtl construction for simulation so we will not
// tag it with a @[fileinfo] tag as it doesn't directly correspond to
// a specific line of verilog code.
- wire_decls.push_back(stringf(" %s is invalid\n", make_id(wire->name)));
+ wire_decls.push_back(stringf("%s%s is invalid\n", indent.c_str(), make_id(wire->name)));
}
}
@@ -1112,12 +1347,7 @@ struct FirrtlWorker
void run()
{
- // Blackboxes should be emitted as `extmodule`s in firrtl. Only ports are
- // emitted in such a case.
- if (module->get_blackbox_attribute())
- emit_extmodule();
- else
- emit_module();
+ emit_module();
}
};
@@ -1180,10 +1410,16 @@ struct FirrtlBackend : public Backend {
std::string circuitFileinfo = getFileinfo(top);
*f << stringf("circuit %s: %s\n", make_id(top->name), circuitFileinfo.c_str());
+ emit_elaborated_extmodules(design, *f);
+
+ // Emit non-blackbox modules.
for (auto module : design->modules())
{
- FirrtlWorker worker(module, *f, design);
- worker.run();
+ if (!module->get_blackbox_attribute())
+ {
+ FirrtlWorker worker(module, *f, design);
+ worker.run();
+ }
}
namecache.clear();
diff --git a/kernel/driver.cc b/kernel/driver.cc
index 57ed7b8b4..b55f02837 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -267,9 +267,11 @@ int main(int argc, char **argv)
printf("\n");
printf(" -s scriptfile\n");
printf(" execute the commands in the script file\n");
+#ifdef YOSYS_ENABLE_TCL
printf("\n");
printf(" -c tcl_scriptfile\n");
printf(" execute the commands in the tcl script file (see 'help tcl' for details)\n");
+#endif
printf("\n");
printf(" -p command\n");
printf(" execute the commands\n");
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 7a2ef4913..dcaf364e9 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -89,6 +89,12 @@ bool memhasher_active = false;
uint32_t memhasher_rng = 123456;
std::vector<void*> memhasher_store;
+std::string yosys_share_dirname;
+std::string yosys_abc_executable;
+
+void init_share_dirname();
+void init_abc_executable_name();
+
void memhasher_on()
{
#if defined(__linux__) || defined(__FreeBSD__)
@@ -523,6 +529,8 @@ void yosys_setup()
if(already_setup)
return;
already_setup = true;
+ init_share_dirname();
+ init_abc_executable_name();
#define X(_id) RTLIL::ID::_id = "\\" # _id;
#include "kernel/constids.inc"
@@ -825,38 +833,74 @@ std::string proc_self_dirname()
#endif
#if defined(EMSCRIPTEN) || defined(__wasm)
-std::string proc_share_dirname()
+void init_share_dirname()
{
- return "/share/";
+ yosys_share_dirname = "/share/";
}
#else
-std::string proc_share_dirname()
+void init_share_dirname()
{
std::string proc_self_path = proc_self_dirname();
# if defined(_WIN32) && !defined(YOSYS_WIN32_UNIX_DIR)
std::string proc_share_path = proc_self_path + "share\\";
- if (check_file_exists(proc_share_path, true))
- return proc_share_path;
+ if (check_file_exists(proc_share_path, true)) {
+ yosys_share_dirname = proc_share_path;
+ return;
+ }
proc_share_path = proc_self_path + "..\\share\\";
- if (check_file_exists(proc_share_path, true))
- return proc_share_path;
+ if (check_file_exists(proc_share_path, true)) {
+ yosys_share_dirname = proc_share_path;
+ return;
+ }
# else
std::string proc_share_path = proc_self_path + "share/";
- if (check_file_exists(proc_share_path, true))
- return proc_share_path;
+ if (check_file_exists(proc_share_path, true)) {
+ yosys_share_dirname = proc_share_path;
+ return;
+ }
proc_share_path = proc_self_path + "../share/" + proc_program_prefix()+ "yosys/";
- if (check_file_exists(proc_share_path, true))
- return proc_share_path;
+ if (check_file_exists(proc_share_path, true)) {
+ yosys_share_dirname = proc_share_path;
+ return;
+ }
# ifdef YOSYS_DATDIR
proc_share_path = YOSYS_DATDIR "/";
- if (check_file_exists(proc_share_path, true))
- return proc_share_path;
+ if (check_file_exists(proc_share_path, true)) {
+ yosys_share_dirname = proc_share_path;
+ return;
+ }
# endif
# endif
- log_error("proc_share_dirname: unable to determine share/ directory!\n");
}
#endif
+void init_abc_executable_name()
+{
+#ifdef ABCEXTERNAL
+ std::string exe_file;
+ if (std::getenv("ABC")) {
+ yosys_abc_executable = std::getenv("ABC");
+ } else {
+ yosys_abc_executable = ABCEXTERNAL;
+ }
+#else
+ yosys_abc_executable = proc_self_dirname() + proc_program_prefix()+ "yosys-abc";
+#endif
+#ifdef _WIN32
+#ifndef ABCEXTERNAL
+ if (!check_file_exists(yosys_abc_executable + ".exe") && check_file_exists(proc_self_dirname() + "..\\" + proc_program_prefix() + "yosys-abc.exe"))
+ yosys_abc_executable = proc_self_dirname() + "..\\" + proc_program_prefix() + "yosys-abc";
+#endif
+#endif
+}
+
+std::string proc_share_dirname()
+{
+ if (yosys_share_dirname.empty())
+ log_error("init_share_dirname: unable to determine share/ directory!\n");
+ return yosys_share_dirname;
+}
+
std::string proc_program_prefix()
{
std::string program_prefix;
diff --git a/kernel/yosys.h b/kernel/yosys.h
index f1646d6bc..ab6eb5f8c 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -366,6 +366,9 @@ extern std::map<std::string, void*> loaded_python_plugins;
extern std::map<std::string, std::string> loaded_plugin_aliases;
void load_plugin(std::string filename, std::vector<std::string> aliases);
+extern std::string yosys_share_dirname;
+extern std::string yosys_abc_executable;
+
YOSYS_NAMESPACE_END
#endif
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 66ac6828f..192e39372 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1470,16 +1470,7 @@ struct AbcPass : public Pass {
pi_map.clear();
po_map.clear();
-#ifdef ABCEXTERNAL
- std::string exe_file;
- if (std::getenv("ABC")) {
- exe_file = std::getenv("ABC");
- } else {
- exe_file = ABCEXTERNAL;
- }
-#else
- std::string exe_file = proc_self_dirname() + proc_program_prefix() + "yosys-abc";
-#endif
+ std::string exe_file = yosys_abc_executable;
std::string script_file, liberty_file, constr_file, clk_str;
std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
@@ -1494,13 +1485,6 @@ struct AbcPass : public Pass {
enabled_gates.clear();
cmos_cost = false;
-#ifdef _WIN32
-#ifndef ABCEXTERNAL
- if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\" + proc_program_prefix()+ "yosys-abc.exe"))
- exe_file = proc_self_dirname() + "..\\" + proc_program_prefix() + "yosys-abc";
-#endif
-#endif
-
// get arguments from scratchpad first, then override by command arguments
std::string lut_arg, luts_arg, g_arg;
exe_file = design->scratchpad_get_string("abc.exe", exe_file /* inherit default value if not set */);
diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc
index 7355840aa..b916b049d 100644
--- a/passes/techmap/abc9_exe.cc
+++ b/passes/techmap/abc9_exe.cc
@@ -379,11 +379,7 @@ struct Abc9ExePass : public Pass {
{
log_header(design, "Executing ABC9_EXE pass (technology mapping using ABC9).\n");
-#ifdef ABCEXTERNAL
- std::string exe_file = ABCEXTERNAL;
-#else
- std::string exe_file = proc_self_dirname() + proc_program_prefix()+ "yosys-abc";
-#endif
+ std::string exe_file = yosys_abc_executable;
std::string script_file, clk_str, box_file, lut_file;
std::string delay_target, lutin_shared = "-S 1", wire_delay;
std::string tempdir_name;
@@ -396,13 +392,6 @@ struct Abc9ExePass : public Pass {
show_tempdir = true;
#endif
-#ifdef _WIN32
-#ifndef ABCEXTERNAL
- if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\" + proc_program_prefix() + "yosys-abc.exe"))
- exe_file = proc_self_dirname() + "..\\" + proc_program_prefix() + "yosys-abc";
-#endif
-#endif
-
std::string lut_arg, luts_arg;
exe_file = design->scratchpad_get_string("abc9.exe", exe_file /* inherit default value if not set */);
script_file = design->scratchpad_get_string("abc9.script", script_file);
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 47ece84df..509bf3ef2 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -821,3 +821,48 @@ endspecify
endmodule
+(* blackbox *)
+module rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);
+input CLKIN;
+input CLKFB;
+input RESET;
+input RESET_P;
+input [5:0] FBDSEL;
+input [5:0] IDSEL;
+input [5:0] ODSEL;
+input [3:0] PSDA,FDLY;
+input [3:0] DUTYDA;
+
+output CLKOUT;
+output LOCK;
+output CLKOUTP;
+output CLKOUTD;
+output CLKOUTD3;
+
+parameter FCLKIN = "100.0"; // frequency of CLKIN
+parameter DYN_IDIV_SEL= "false"; // true:IDSEL, false:IDIV_SEL
+parameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64
+parameter DYN_FBDIV_SEL= "false"; // true:FBDSEL, false:FBDIV_SEL
+parameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64
+parameter DYN_ODIV_SEL= "false"; // true:ODSEL, false:ODIV_SEL
+parameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128
+
+parameter PSDA_SEL= "0000";
+parameter DYN_DA_EN = "false"; // true:PSDA or DUTYDA or FDA, false: DA_SEL
+parameter DUTYDA_SEL= "1000";
+
+parameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only
+parameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only
+parameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4
+parameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2
+
+parameter CLKFB_SEL = "internal"; // "internal", "external"
+parameter CLKOUT_BYPASS = "false"; // "true", "false"
+parameter CLKOUTP_BYPASS = "false"; // "true", "false"
+parameter CLKOUTD_BYPASS = "false"; // "true", "false"
+parameter DYN_SDIV_SEL = 2; // 2~128, only even numbers
+parameter CLKOUTD_SRC = "CLKOUT"; // CLKOUT, CLKOUTP
+parameter CLKOUTD3_SRC = "CLKOUT"; // CLKOUT, CLKOUTP
+parameter DEVICE = "GW1N-1"; // "GW1N-1", "GW1N-4", "GW1N-9", "GW1NR-4", "GW1NR-9", "GW1N-4B", "GW1NR-4B", "GW1NS-2", "GW1NS-2C", "GW1NZ-1", "GW1NSR-2", "GW1NSR-2C", "GW1N-1S", "GW1NSE-2C", "GW1NRF-4B", "GW1N-9C", "GW1NR-9C", "GW1N-4C", "GW1NR-4C"
+
+endmodule
diff --git a/techlibs/intel/common/m9k_bb.v b/techlibs/intel/common/m9k_bb.v
index b18a752f5..4bb230642 100644
--- a/techlibs/intel/common/m9k_bb.v
+++ b/techlibs/intel/common/m9k_bb.v
@@ -32,7 +32,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
parameter outdata_reg_a = "UNREGISTERED";
parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA";
- parameter outdata_reg_a = "UNREGISTERED";
+ parameter outdata_reg_b = "UNREGISTERED";
parameter lpm_type = "altsyncram";
parameter init_type = "unused";
parameter ram_block_type = "AUTO";
diff --git a/techlibs/nexus/Makefile.inc b/techlibs/nexus/Makefile.inc
index e0ff40e15..c9a9ad4ff 100644
--- a/techlibs/nexus/Makefile.inc
+++ b/techlibs/nexus/Makefile.inc
@@ -11,4 +11,5 @@ $(eval $(call add_share_file,share/nexus,techlibs/nexus/brams_map.v))
$(eval $(call add_share_file,share/nexus,techlibs/nexus/brams.txt))
$(eval $(call add_share_file,share/nexus,techlibs/nexus/arith_map.v))
$(eval $(call add_share_file,share/nexus,techlibs/nexus/latches_map.v))
+$(eval $(call add_share_file,share/nexus,techlibs/nexus/dsp_map.v))
diff --git a/techlibs/nexus/cells_sim.v b/techlibs/nexus/cells_sim.v
index 41c8a3c73..b5938e08f 100644
--- a/techlibs/nexus/cells_sim.v
+++ b/techlibs/nexus/cells_sim.v
@@ -377,3 +377,567 @@ module DPR16X4(
mem[WAD] <= DI;
assign DO = mem[RAD];
endmodule
+
+// Used for all the DSP models to reduce duplication
+module OXIDE_DSP_REG #(
+ parameter W = 18,
+ parameter USED = "REGISTER",
+ parameter RESETMODE = "SYNC"
+) (
+ input CLK, CE, RST,
+ input [W-1:0] D,
+ output reg [W-1:0] Q
+);
+ generate
+ if (USED == "BYPASS")
+ always @* Q = D;
+ else if (USED == "REGISTER") begin
+ initial Q = 0;
+ if (RESETMODE == "ASYNC")
+ always @(posedge CLK, posedge RST) begin
+ if (RST)
+ Q <= 0;
+ else if (CE)
+ Q <= D;
+ end
+ else if (RESETMODE == "SYNC")
+ always @(posedge CLK) begin
+ if (RST)
+ Q <= 0;
+ else if (CE)
+ Q <= D;
+ end
+ end
+ endgenerate
+endmodule
+
+module OXIDE_DSP_SIM #(
+ // User facing parameters
+ parameter REGINPUTA = "BYPASS",
+ parameter REGINPUTB = "BYPASS",
+ parameter REGINPUTC = "BYPASS",
+ parameter REGADDSUB = "BYPASS",
+ parameter REGLOADC = "BYPASS",
+ parameter REGLOADC2 = "BYPASS",
+ parameter REGCIN = "BYPASS",
+ parameter REGPIPELINE = "BYPASS",
+ parameter REGOUTPUT = "BYPASS",
+ parameter GSR = "ENABLED",
+ parameter RESETMODE = "SYNC",
+ // Internally used parameters
+ parameter A_WIDTH = 36,
+ parameter B_WIDTH = 36,
+ parameter C_WIDTH = 36,
+ parameter Z_WIDTH = 72,
+ parameter PREADD_USED = 0,
+ parameter ADDSUB_USED = 0
+) (
+ input [A_WIDTH-1:0] A,
+ input [B_WIDTH-1:0] B,
+ input [C_WIDTH-1:0] C,
+ input SIGNEDA,
+ input SIGNEDB,
+ input SIGNEDC,
+ input CIN,
+ input LOADC,
+ input ADDSUB,
+ input CLK,
+ input CEA, CEB, CEC, CEPIPE, CECTRL, CECIN, CEOUT,
+ input RSTA, RSTB, RSTC, RSTPIPE, RSTCTRL, RSTCIN, RSTOUT,
+ output wire [Z_WIDTH-1:0] Z
+);
+
+ localparam M_WIDTH = (A_WIDTH+B_WIDTH);
+
+ /******** REGISTERS ********/
+
+ wire [M_WIDTH-1:0] pipe_d, pipe_q;
+ wire [Z_WIDTH-1:0] z_d;
+
+ wire [A_WIDTH-1:0] a_r;
+ wire [B_WIDTH-1:0] b_r;
+ wire [C_WIDTH-1:0] c_r, c_r2;
+ wire asgd_r, bsgd_r, csgd_r, csgd_r2;
+
+ wire addsub_r, addsub_r2, cin_r, cin_r2, sgd_r, sgd_r2;
+ wire loadc_r, loadc_r2;
+
+ OXIDE_DSP_REG #(A_WIDTH+1, REGINPUTA, RESETMODE) a_reg(CLK, CEA, RSTA, {SIGNEDA, A}, {asgd_r, a_r});
+ OXIDE_DSP_REG #(B_WIDTH+1, REGINPUTB, RESETMODE) b_reg(CLK, CEB, RSTB, {SIGNEDB, B}, {bsgd_r, b_r});
+ OXIDE_DSP_REG #(C_WIDTH+1, REGINPUTC, RESETMODE) c_reg(CLK, CEC, RSTC, {SIGNEDC, C}, {csgd_r, c_r});
+
+ OXIDE_DSP_REG #(M_WIDTH, REGPIPELINE, RESETMODE) pipe_reg(CLK, CEPIPE, RSTPIPE, pipe_d, pipe_q);
+
+ OXIDE_DSP_REG #(2, REGADDSUB, RESETMODE) addsub_reg(CLK, CECTRL, RSTCTRL, {SIGNEDA, ADDSUB}, {sgd_r, addsub_r});
+ OXIDE_DSP_REG #(1, REGLOADC, RESETMODE) loadc_reg(CLK, CECTRL, RSTCTRL, LOADC, loadc_r);
+ OXIDE_DSP_REG #(2, REGPIPELINE, RESETMODE) addsub2_reg(CLK, CECTRL, RSTCTRL, {sgd_r, addsub_r}, {sgd_r2, addsub_r2});
+ OXIDE_DSP_REG #(1, REGLOADC2, RESETMODE) loadc2_reg(CLK, CECTRL, RSTCTRL, loadc_r, loadc_r2);
+
+ OXIDE_DSP_REG #(1, REGCIN, RESETMODE) cin_reg(CLK, CECIN, RSTCIN, CIN, cin_r);
+ OXIDE_DSP_REG #(1, REGPIPELINE, RESETMODE) cin2_reg(CLK, CECIN, RSTCIN, cin_r, cin_r2);
+
+ OXIDE_DSP_REG #(C_WIDTH+1, REGPIPELINE, RESETMODE) c2_reg(CLK, CEC, RSTC, {csgd_r, c_r}, {csgd_r2, c_r2});
+
+ OXIDE_DSP_REG #(Z_WIDTH, REGOUTPUT, RESETMODE) z_reg(CLK, CEOUT, RSTOUT, z_d, Z);
+
+ /******** PREADDER ********/
+
+ wire [B_WIDTH-1:0] mult_b;
+ wire mult_b_sgd;
+
+ generate
+ if (PREADD_USED) begin
+ assign mult_b = (b_r + c_r);
+ assign mult_b_sgd = (bsgd_r | csgd_r);
+ end else begin
+ assign mult_b = b_r;
+ assign mult_b_sgd = bsgd_r;
+ end
+ endgenerate
+
+ /******** MULTIPLIER ********/
+
+ // sign extend operands if needed
+ wire [M_WIDTH-1:0] mult_a_ext = {{(M_WIDTH-A_WIDTH){asgd_r ? a_r[A_WIDTH-1] : 1'b0}}, a_r};
+ wire [M_WIDTH-1:0] mult_b_ext = {{(M_WIDTH-B_WIDTH){mult_b_sgd ? mult_b[B_WIDTH-1] : 1'b0}}, mult_b};
+
+ wire [M_WIDTH-1:0] mult_m = mult_a_ext * mult_b_ext;
+
+ /******** ACCUMULATOR ********/
+
+ wire [Z_WIDTH-1:0] m_ext;
+
+ generate
+ if (ADDSUB_USED) begin
+ assign pipe_d = mult_m;
+ assign m_ext = {{(Z_WIDTH-M_WIDTH){sgd_r2 ? pipe_q[M_WIDTH-1] : 1'b0}}, pipe_q};
+ assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);
+ end else begin
+ assign z_d = mult_m;
+ end
+ endgenerate
+
+
+endmodule
+
+module MULT9X9 #(
+ parameter REGINPUTA = "REGISTER",
+ parameter REGINPUTB = "REGISTER",
+ parameter REGOUTPUT = "REGISTER",
+ parameter GSR = "ENABLED",
+ parameter RESETMODE = "SYNC"
+) (
+ input [8:0] A,
+ input [8:0] B,
+ input CLK,
+ input CEA,
+ input RSTA,
+ input CEB,
+ input RSTB,
+ input SIGNEDA,
+ input SIGNEDB,
+ input RSTOUT,
+ input CEOUT,
+ output [17:0] Z
+);
+ OXIDE_DSP_SIM #(
+ .REGINPUTA(REGINPUTA),
+ .REGINPUTB(REGINPUTB),
+ .REGOUTPUT(REGOUTPUT),
+ .GSR(GSR),
+ .RESETMODE(RESETMODE),
+
+ .A_WIDTH(9),
+ .B_WIDTH(9),
+ .Z_WIDTH(18),
+ .PREADD_USED(0),
+ .ADDSUB_USED(0)
+ ) dsp_i (
+ .A(A), .B(B),
+ .CLK(CLK),
+ .CEA(CEA), .RSTA(RSTA),
+ .CEB(CEB), .RSTB(RSTB),
+ .SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
+ .RSTOUT(RSTOUT), .CEOUT(CEOUT),
+ .Z(Z)
+ );
+endmodule
+
+module MULT18X18 #(
+ parameter REGINPUTA = "REGISTER",
+ parameter REGINPUTB = "REGISTER",
+ parameter REGOUTPUT = "REGISTER",
+ parameter GSR = "ENABLED",
+ parameter RESETMODE = "SYNC"
+) (
+ input [17:0] A,
+ input [17:0] B,
+ input CLK,
+ input CEA,
+ input RSTA,
+ input CEB,
+ input RSTB,
+ input SIGNEDA,
+ input SIGNEDB,
+ input RSTOUT,
+ input CEOUT,
+ output [35:0] Z
+);
+ OXIDE_DSP_SIM #(
+ .REGINPUTA(REGINPUTA),
+ .REGINPUTB(REGINPUTB),
+ .REGOUTPUT(REGOUTPUT),
+ .GSR(GSR),
+ .RESETMODE(RESETMODE),
+
+ .A_WIDTH(18),
+ .B_WIDTH(18),
+ .Z_WIDTH(36),
+ .PREADD_USED(0),
+ .ADDSUB_USED(0)
+ ) dsp_i (
+ .A(A), .B(B),
+ .CLK(CLK),
+ .CEA(CEA), .RSTA(RSTA),
+ .CEB(CEB), .RSTB(RSTB),
+ .SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
+ .RSTOUT(RSTOUT), .CEOUT(CEOUT),
+ .Z(Z)
+ );
+endmodule
+
+module MULT18X36 #(
+ parameter REGINPUTA = "REGISTER",
+ parameter REGINPUTB = "REGISTER",
+ parameter REGOUTPUT = "REGISTER",
+ parameter GSR = "ENABLED",
+ parameter RESETMODE = "SYNC"
+) (
+ input [17:0] A,
+ input [35:0] B,
+ input CLK,
+ input CEA,
+ input RSTA,
+ input CEB,
+ input RSTB,
+ input SIGNEDA,
+ input SIGNEDB,
+ input RSTOUT,
+ input CEOUT,
+ output [53:0] Z
+);
+ OXIDE_DSP_SIM #(
+ .REGINPUTA(REGINPUTA),
+ .REGINPUTB(REGINPUTB),
+ .REGOUTPUT(REGOUTPUT),
+ .GSR(GSR),
+ .RESETMODE(RESETMODE),
+
+ .A_WIDTH(18),
+ .B_WIDTH(36),
+ .Z_WIDTH(54),
+ .PREADD_USED(0),
+ .ADDSUB_USED(0)
+ ) dsp_i (
+ .A(A), .B(B),
+ .CLK(CLK),
+ .CEA(CEA), .RSTA(RSTA),
+ .CEB(CEB), .RSTB(RSTB),
+ .SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
+ .RSTOUT(RSTOUT), .CEOUT(CEOUT),
+ .Z(Z)
+ );
+endmodule
+
+module MULT36X36 #(
+ parameter REGINPUTA = "REGISTER",
+ parameter REGINPUTB = "REGISTER",
+ parameter REGOUTPUT = "REGISTER",
+ parameter GSR = "ENABLED",
+ parameter RESETMODE = "SYNC"
+) (
+ input [35:0] A,
+ input [35:0] B,
+ input CLK,
+ input CEA,
+ input RSTA,
+ input CEB,
+ input RSTB,
+ input SIGNEDA,
+ input SIGNEDB,
+ input RSTOUT,
+ input CEOUT,
+ output [71:0] Z
+);
+ OXIDE_DSP_SIM #(
+ .REGINPUTA(REGINPUTA),
+ .REGINPUTB(REGINPUTB),
+ .REGOUTPUT(REGOUTPUT),
+ .GSR(GSR),
+ .RESETMODE(RESETMODE),
+
+ .A_WIDTH(36),
+ .B_WIDTH(36),
+ .Z_WIDTH(72),
+ .PREADD_USED(0),
+ .ADDSUB_USED(0)
+ ) dsp_i (
+ .A(A), .B(B),
+ .CLK(CLK),
+ .CEA(CEA), .RSTA(RSTA),
+ .CEB(CEB), .RSTB(RSTB),
+ .SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
+ .RSTOUT(RSTOUT), .CEOUT(CEOUT),
+ .Z(Z)
+ );
+endmodule
+
+
+module MULTPREADD9X9 #(
+ parameter REGINPUTA = "REGISTER",
+ parameter REGINPUTB = "REGISTER",
+ parameter REGINPUTC = "REGISTER",
+ parameter REGOUTPUT = "REGISTER",
+ parameter GSR = "ENABLED",
+ parameter RESETMODE = "SYNC"
+) (
+ input [8:0] A,
+ input [8:0] B,
+ input [8:0] C,
+ input CLK,
+ input CEA,
+ input RSTA,
+ input CEB,
+ input RSTB,
+ input CEC,
+ input RSTC,
+ input SIGNEDA,
+ input SIGNEDB,
+ input SIGNEDC,
+ input RSTOUT,
+ input CEOUT,
+ output [17:0] Z
+);
+ OXIDE_DSP_SIM #(
+ .REGINPUTA(REGINPUTA),
+ .REGINPUTB(REGINPUTB),
+ .REGINPUTC(REGINPUTC),
+ .REGOUTPUT(REGOUTPUT),
+ .GSR(GSR),
+ .RESETMODE(RESETMODE),
+
+ .A_WIDTH(9),
+ .B_WIDTH(9),
+ .C_WIDTH(9),
+ .Z_WIDTH(18),
+ .PREADD_USED(1),
+ .ADDSUB_USED(0)
+ ) dsp_i (
+ .A(A), .B(B), .C(C),
+ .CLK(CLK),
+ .CEA(CEA), .RSTA(RSTA),
+ .CEB(CEB), .RSTB(RSTB),
+ .CEC(CEC), .RSTC(RSTC),
+ .SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB), .SIGNEDC(SIGNEDC),
+ .RSTOUT(RSTOUT), .CEOUT(CEOUT),
+ .Z(Z)
+ );
+endmodule
+
+
+module MULTPREADD18X18 #(
+ parameter REGINPUTA = "REGISTER",
+ parameter REGINPUTB = "REGISTER",
+ parameter REGINPUTC = "REGISTER",
+ parameter REGOUTPUT = "REGISTER",
+ parameter GSR = "ENABLED",
+ parameter RESETMODE = "SYNC"
+) (
+ input [17:0] A,
+ input [17:0] B,
+ input [17:0] C,
+ input CLK,
+ input CEA,
+ input RSTA,
+ input CEB,
+ input RSTB,
+ input CEC,
+ input RSTC,
+ input SIGNEDA,
+ input SIGNEDB,
+ input SIGNEDC,
+ input RSTOUT,
+ input CEOUT,
+ output [35:0] Z
+);
+ OXIDE_DSP_SIM #(
+ .REGINPUTA(REGINPUTA),
+ .REGINPUTB(REGINPUTB),
+ .REGINPUTC(REGINPUTC),
+ .REGOUTPUT(REGOUTPUT),
+ .GSR(GSR),
+ .RESETMODE(RESETMODE),
+
+ .A_WIDTH(18),
+ .B_WIDTH(18),
+ .C_WIDTH(18),
+ .Z_WIDTH(36),
+ .PREADD_USED(1),
+ .ADDSUB_USED(0)
+ ) dsp_i (
+ .A(A), .B(B), .C(C),
+ .CLK(CLK),
+ .CEA(CEA), .RSTA(RSTA),
+ .CEB(CEB), .RSTB(RSTB),
+ .CEC(CEC), .RSTC(RSTC),
+ .SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB), .SIGNEDC(SIGNEDC),
+ .RSTOUT(RSTOUT), .CEOUT(CEOUT),
+ .Z(Z)
+ );
+endmodule
+
+
+module MULTADDSUB18X18 #(
+ parameter REGINPUTA = "REGISTER",
+ parameter REGINPUTB = "REGISTER",
+ parameter REGINPUTC = "REGISTER",
+ parameter REGADDSUB = "REGISTER",
+ parameter REGLOADC = "REGISTER",
+ parameter REGLOADC2 = "REGISTER",
+ parameter REGCIN = "REGISTER",
+ parameter REGPIPELINE = "REGISTER",
+ parameter REGOUTPUT = "REGISTER",
+ parameter GSR = "ENABLED",
+ parameter RESETMODE = "SYNC"
+) (
+ input [17:0] A,
+ input [17:0] B,
+ input [53:0] C,
+ input CLK,
+ input CEA,
+ input RSTA,
+ input CEB,
+ input RSTB,
+ input CEC,
+ input RSTC,
+ input SIGNED,
+ input RSTPIPE,
+ input CEPIPE,
+ input RSTCTRL,
+ input CECTRL,
+ input RSTCIN,
+ input CECIN,
+ input LOADC,
+ input ADDSUB,
+ output [53:0] Z,
+ input RSTOUT,
+ input CEOUT,
+ input CIN
+);
+ OXIDE_DSP_SIM #(
+ .REGINPUTA(REGINPUTA),
+ .REGINPUTB(REGINPUTB),
+ .REGINPUTC(REGINPUTC),
+ .REGADDSUB(REGADDSUB),
+ .REGLOADC(REGLOADC),
+ .REGLOADC2(REGLOADC2),
+ .REGCIN(REGCIN),
+ .REGPIPELINE(REGPIPELINE),
+ .REGOUTPUT(REGOUTPUT),
+ .GSR(GSR),
+ .RESETMODE(RESETMODE),
+
+ .A_WIDTH(18),
+ .B_WIDTH(18),
+ .C_WIDTH(54),
+ .Z_WIDTH(54),
+ .PREADD_USED(0),
+ .ADDSUB_USED(1)
+ ) dsp_i (
+ .A(A), .B(B), .C(C),
+ .CLK(CLK),
+ .CEA(CEA), .RSTA(RSTA),
+ .CEB(CEB), .RSTB(RSTB),
+ .CEC(CEC), .RSTC(RSTC),
+ .CEPIPE(CEPIPE), .RSTPIPE(RSTPIPE),
+ .CECTRL(CECTRL), .RSTCTRL(RSTCTRL),
+ .CECIN(CECIN), .RSTCIN(RSTCIN),
+ .CIN(CIN), .LOADC(LOADC), .ADDSUB(ADDSUB),
+ .SIGNEDA(SIGNED), .SIGNEDB(SIGNED), .SIGNEDC(SIGNED),
+ .RSTOUT(RSTOUT), .CEOUT(CEOUT),
+ .Z(Z)
+ );
+endmodule
+
+
+module MULTADDSUB36X36 #(
+ parameter REGINPUTA = "REGISTER",
+ parameter REGINPUTB = "REGISTER",
+ parameter REGINPUTC = "REGISTER",
+ parameter REGADDSUB = "REGISTER",
+ parameter REGLOADC = "REGISTER",
+ parameter REGLOADC2 = "REGISTER",
+ parameter REGCIN = "REGISTER",
+ parameter REGPIPELINE = "REGISTER",
+ parameter REGOUTPUT = "REGISTER",
+ parameter GSR = "ENABLED",
+ parameter RESETMODE = "SYNC"
+) (
+ input [35:0] A,
+ input [35:0] B,
+ input [107:0] C,
+ input CLK,
+ input CEA,
+ input RSTA,
+ input CEB,
+ input RSTB,
+ input CEC,
+ input RSTC,
+ input SIGNED,
+ input RSTPIPE,
+ input CEPIPE,
+ input RSTCTRL,
+ input CECTRL,
+ input RSTCIN,
+ input CECIN,
+ input LOADC,
+ input ADDSUB,
+ output [107:0] Z,
+ input RSTOUT,
+ input CEOUT,
+ input CIN
+);
+ OXIDE_DSP_SIM #(
+ .REGINPUTA(REGINPUTA),
+ .REGINPUTB(REGINPUTB),
+ .REGINPUTC(REGINPUTC),
+ .REGADDSUB(REGADDSUB),
+ .REGLOADC(REGLOADC),
+ .REGLOADC2(REGLOADC2),
+ .REGCIN(REGCIN),
+ .REGPIPELINE(REGPIPELINE),
+ .REGOUTPUT(REGOUTPUT),
+ .GSR(GSR),
+ .RESETMODE(RESETMODE),
+
+ .A_WIDTH(36),
+ .B_WIDTH(36),
+ .C_WIDTH(108),
+ .Z_WIDTH(108),
+ .PREADD_USED(0),
+ .ADDSUB_USED(1)
+ ) dsp_i (
+ .A(A), .B(B), .C(C),
+ .CLK(CLK),
+ .CEA(CEA), .RSTA(RSTA),
+ .CEB(CEB), .RSTB(RSTB),
+ .CEC(CEC), .RSTC(RSTC),
+ .CEPIPE(CEPIPE), .RSTPIPE(RSTPIPE),
+ .CECTRL(CECTRL), .RSTCTRL(RSTCTRL),
+ .CECIN(CECIN), .RSTCIN(RSTCIN),
+ .CIN(CIN), .LOADC(LOADC), .ADDSUB(ADDSUB),
+ .SIGNEDA(SIGNED), .SIGNEDB(SIGNED), .SIGNEDC(SIGNED),
+ .RSTOUT(RSTOUT), .CEOUT(CEOUT),
+ .Z(Z)
+ );
+endmodule
diff --git a/techlibs/nexus/cells_xtra.py b/techlibs/nexus/cells_xtra.py
index dc462c29a..6ced76950 100644
--- a/techlibs/nexus/cells_xtra.py
+++ b/techlibs/nexus/cells_xtra.py
@@ -74,20 +74,20 @@ devices = [
Cell("M18X36"),
Cell("MIPI"),
Cell("MULT18"),
- Cell("MULT18X18"),
- Cell("MULT18X36"),
+# Cell("MULT18X18"),
+# Cell("MULT18X36"),
Cell("MULT36"),
- Cell("MULT36X36"),
+# Cell("MULT36X36"),
Cell("MULT9"),
- Cell("MULT9X9"),
- Cell("MULTADDSUB18X18"),
+# Cell("MULT9X9"),
+# Cell("MULTADDSUB18X18"),
Cell("MULTADDSUB18X18WIDE"),
- Cell("MULTADDSUB18X36"),
- Cell("MULTADDSUB36X36"),
+# Cell("MULTADDSUB18X36"),
+# Cell("MULTADDSUB36X36"),
Cell("MULTADDSUB9X9WIDE"),
Cell("MULTIBOOT", keep=True),
- Cell("MULTPREADD18X18"),
- Cell("MULTPREADD9X9"),
+# Cell("MULTPREADD18X18"),
+# Cell("MULTPREADD9X9"),
Cell("ODDR71"),
Cell("ODDRX1"),
Cell("ODDRX2DQS"),
diff --git a/techlibs/nexus/cells_xtra.v b/techlibs/nexus/cells_xtra.v
index b275e610a..6cf3a645d 100644
--- a/techlibs/nexus/cells_xtra.v
+++ b/techlibs/nexus/cells_xtra.v
@@ -2114,46 +2114,6 @@ module MULT18 (...);
input ROUNDEN;
endmodule
-module MULT18X18 (...);
- parameter REGINPUTA = "REGISTER";
- parameter REGINPUTB = "REGISTER";
- parameter REGOUTPUT = "REGISTER";
- parameter GSR = "ENABLED";
- parameter RESETMODE = "SYNC";
- input [17:0] A;
- input [17:0] B;
- input CLK;
- input CEA;
- input RSTA;
- input CEB;
- input RSTB;
- input SIGNEDA;
- input SIGNEDB;
- input RSTOUT;
- input CEOUT;
- output [35:0] Z;
-endmodule
-
-module MULT18X36 (...);
- parameter REGINPUTA = "REGISTER";
- parameter REGINPUTB = "REGISTER";
- parameter REGOUTPUT = "REGISTER";
- parameter GSR = "ENABLED";
- parameter RESETMODE = "SYNC";
- input [17:0] A;
- input [35:0] B;
- input CLK;
- input CEA;
- input RSTA;
- input CEB;
- input RSTB;
- input SIGNEDA;
- input SIGNEDB;
- input RSTOUT;
- input CEOUT;
- output [53:0] Z;
-endmodule
-
module MULT36 (...);
parameter MULT36X36 = "ENABLED";
input [72:0] PH72;
@@ -2162,26 +2122,6 @@ module MULT36 (...);
output [71:0] PMH72;
endmodule
-module MULT36X36 (...);
- parameter REGINPUTA = "REGISTER";
- parameter REGINPUTB = "REGISTER";
- parameter REGOUTPUT = "REGISTER";
- parameter GSR = "ENABLED";
- parameter RESETMODE = "SYNC";
- input [35:0] A;
- input [35:0] B;
- input CLK;
- input CEA;
- input RSTA;
- input CEB;
- input RSTB;
- input SIGNEDA;
- input SIGNEDB;
- input RSTOUT;
- input CEOUT;
- output [71:0] Z;
-endmodule
-
module MULT9 (...);
parameter SIGNEDSTATIC_EN = "DISABLED";
parameter ASIGNED_OPERAND_EN = "DISABLED";
@@ -2215,63 +2155,6 @@ module MULT9 (...);
input RSTP;
endmodule
-module MULT9X9 (...);
- parameter REGINPUTA = "REGISTER";
- parameter REGINPUTB = "REGISTER";
- parameter REGOUTPUT = "REGISTER";
- parameter GSR = "ENABLED";
- parameter RESETMODE = "SYNC";
- input [8:0] A;
- input [8:0] B;
- input CLK;
- input CEA;
- input RSTA;
- input CEB;
- input RSTB;
- input SIGNEDA;
- input SIGNEDB;
- input RSTOUT;
- input CEOUT;
- output [17:0] Z;
-endmodule
-
-module MULTADDSUB18X18 (...);
- parameter REGINPUTA = "REGISTER";
- parameter REGINPUTB = "REGISTER";
- parameter REGINPUTC = "REGISTER";
- parameter REGADDSUB = "REGISTER";
- parameter REGLOADC = "REGISTER";
- parameter REGLOADC2 = "REGISTER";
- parameter REGCIN = "REGISTER";
- parameter REGPIPELINE = "REGISTER";
- parameter REGOUTPUT = "REGISTER";
- parameter GSR = "ENABLED";
- parameter RESETMODE = "SYNC";
- input [17:0] A;
- input [17:0] B;
- input [53:0] C;
- input CLK;
- input CEA;
- input RSTA;
- input CEB;
- input RSTB;
- input CEC;
- input RSTC;
- input SIGNED;
- input RSTPIPE;
- input CEPIPE;
- input RSTCTRL;
- input CECTRL;
- input RSTCIN;
- input CECIN;
- input LOADC;
- input ADDSUB;
- output [53:0] Z;
- input RSTOUT;
- input CEOUT;
- input CIN;
-endmodule
-
module MULTADDSUB18X18WIDE (...);
parameter REGINPUTAB0 = "REGISTER";
parameter REGINPUTAB1 = "REGISTER";
@@ -2311,80 +2194,6 @@ module MULTADDSUB18X18WIDE (...);
input [1:0] ADDSUB;
endmodule
-module MULTADDSUB18X36 (...);
- parameter REGINPUTA = "REGISTER";
- parameter REGINPUTB = "REGISTER";
- parameter REGINPUTC = "REGISTER";
- parameter REGADDSUB = "REGISTER";
- parameter REGLOADC = "REGISTER";
- parameter REGLOADC2 = "REGISTER";
- parameter REGCIN = "REGISTER";
- parameter REGPIPELINE = "REGISTER";
- parameter REGOUTPUT = "REGISTER";
- parameter GSR = "ENABLED";
- parameter RESETMODE = "SYNC";
- input [17:0] A;
- input [35:0] B;
- input [53:0] C;
- input CLK;
- input CEA;
- input RSTA;
- input CEB;
- input RSTB;
- input CEC;
- input RSTC;
- input RSTCTRL;
- input CECTRL;
- input RSTCIN;
- input CECIN;
- input SIGNED;
- input RSTPIPE;
- input CEPIPE;
- input RSTOUT;
- input CEOUT;
- output [53:0] Z;
- input LOADC;
- input ADDSUB;
- input CIN;
-endmodule
-
-module MULTADDSUB36X36 (...);
- parameter REGINPUTA = "REGISTER";
- parameter REGINPUTB = "REGISTER";
- parameter REGINPUTC = "REGISTER";
- parameter REGADDSUB = "REGISTER";
- parameter REGLOADC = "REGISTER";
- parameter REGLOADC2 = "REGISTER";
- parameter REGCIN = "REGISTER";
- parameter REGPIPELINE = "REGISTER";
- parameter REGOUTPUT = "REGISTER";
- parameter GSR = "ENABLED";
- parameter RESETMODE = "SYNC";
- input [35:0] A;
- input [35:0] B;
- input [107:0] C;
- input CLK;
- input CEA;
- input RSTA;
- input CEB;
- input RSTB;
- input CEC;
- input RSTC;
- input RSTCTRL;
- input CECTRL;
- input RSTCIN;
- input CECIN;
- input SIGNED;
- input RSTPIPE;
- input CEPIPE;
- input RSTOUT;
- input CEOUT;
- output [107:0] Z;
- input LOADC;
- input ADDSUB;
- input CIN;
-endmodule
-
module MULTADDSUB9X9WIDE (...);
parameter REGINPUTAB0 = "REGISTER";
parameter REGINPUTAB1 = "REGISTER";
@@ -2438,56 +2247,6 @@ module MULTIBOOT (...);
input [31:0] MSPIMADDR;
endmodule
-module MULTPREADD18X18 (...);
- parameter REGINPUTA = "REGISTER";
- parameter REGINPUTB = "REGISTER";
- parameter REGINPUTC = "REGISTER";
- parameter REGOUTPUT = "REGISTER";
- parameter GSR = "ENABLED";
- parameter RESETMODE = "SYNC";
- input [17:0] A;
- input [17:0] B;
- input [17:0] C;
- input CLK;
- input CEA;
- input RSTA;
- input CEB;
- input RSTB;
- input CEC;
- input RSTC;
- input SIGNEDA;
- input SIGNEDB;
- input SIGNEDC;
- input RSTOUT;
- input CEOUT;
- output [35:0] Z;
-endmodule
-
-module MULTPREADD9X9 (...);
- parameter REGINPUTA = "REGISTER";
- parameter REGINPUTB = "REGISTER";
- parameter REGINPUTC = "REGISTER";
- parameter REGOUTPUT = "REGISTER";
- parameter GSR = "ENABLED";
- parameter RESETMODE = "SYNC";
- input [8:0] A;
- input [8:0] B;
- input [8:0] C;
- input CLK;
- input CEA;
- input RSTA;
- input CEB;
- input RSTB;
- input CEC;
- input RSTC;
- input SIGNEDA;
- input SIGNEDB;
- input SIGNEDC;
- input RSTOUT;
- input CEOUT;
- output [17:0] Z;
-endmodule
-
module ODDR71 (...);
parameter GSR = "ENABLED";
input D0;
diff --git a/techlibs/nexus/dsp_map.v b/techlibs/nexus/dsp_map.v
new file mode 100644
index 000000000..b12528309
--- /dev/null
+++ b/techlibs/nexus/dsp_map.v
@@ -0,0 +1,79 @@
+module \$__NX_MUL36X36 (input [35:0] A, input [35:0] B, output [71:0] Y);
+
+ parameter A_WIDTH = 36;
+ parameter B_WIDTH = 36;
+ parameter Y_WIDTH = 72;
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+
+ MULT36X36 #(
+ .REGINPUTA("BYPASS"),
+ .REGINPUTB("BYPASS"),
+ .REGOUTPUT("BYPASS")
+ ) _TECHMAP_REPLACE_ (
+ .A(A), .B(B),
+ .SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
+ .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
+ .Z(Y)
+ );
+endmodule
+
+module \$__NX_MUL36X18 (input [35:0] A, input [17:0] B, output [53:0] Y);
+
+ parameter A_WIDTH = 36;
+ parameter B_WIDTH = 18;
+ parameter Y_WIDTH = 54;
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+
+ MULT18X36 #(
+ .REGINPUTA("BYPASS"),
+ .REGINPUTB("BYPASS"),
+ .REGOUTPUT("BYPASS")
+ ) _TECHMAP_REPLACE_ (
+ .A(B), .B(A),
+ .SIGNEDA(B_SIGNED ? 1'b1 : 1'b0),
+ .SIGNEDB(A_SIGNED ? 1'b1 : 1'b0),
+ .Z(Y)
+ );
+endmodule
+
+module \$__NX_MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
+
+ parameter A_WIDTH = 18;
+ parameter B_WIDTH = 18;
+ parameter Y_WIDTH = 36;
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+
+ MULT18X18 #(
+ .REGINPUTA("BYPASS"),
+ .REGINPUTB("BYPASS"),
+ .REGOUTPUT("BYPASS")
+ ) _TECHMAP_REPLACE_ (
+ .A(A), .B(B),
+ .SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
+ .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
+ .Z(Y)
+ );
+endmodule
+
+module \$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
+
+ parameter A_WIDTH = 9;
+ parameter B_WIDTH = 9;
+ parameter Y_WIDTH = 18;
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+
+ MULT9X9 #(
+ .REGINPUTA("BYPASS"),
+ .REGINPUTB("BYPASS"),
+ .REGOUTPUT("BYPASS")
+ ) _TECHMAP_REPLACE_ (
+ .A(A), .B(B),
+ .SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
+ .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
+ .Z(Y)
+ );
+endmodule
diff --git a/techlibs/nexus/synth_nexus.cc b/techlibs/nexus/synth_nexus.cc
index 7e2185ab6..9eabbace7 100644
--- a/techlibs/nexus/synth_nexus.cc
+++ b/techlibs/nexus/synth_nexus.cc
@@ -89,6 +89,9 @@ struct SynthNexusPass : public ScriptPass
log(" -noiopad\n");
log(" do not insert IO buffers\n");
log("\n");
+ log(" -nodsp\n");
+ log(" do not infer DSP multipliers\n");
+ log("\n");
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
@@ -98,7 +101,7 @@ struct SynthNexusPass : public ScriptPass
}
string top_opt, json_file, vm_file, family;
- bool noccu2, nodffe, nobram, nolutram, nowidelut, noiopad, flatten, dff, retime, abc9;
+ bool noccu2, nodffe, nobram, nolutram, nowidelut, noiopad, nodsp, flatten, dff, retime, abc9;
void clear_flags() override
{
@@ -112,6 +115,7 @@ struct SynthNexusPass : public ScriptPass
nolutram = false;
nowidelut = false;
noiopad = false;
+ nodsp = false;
flatten = true;
dff = false;
retime = false;
@@ -161,6 +165,10 @@ struct SynthNexusPass : public ScriptPass
dff = true;
continue;
}
+ if (args[argidx] == "-nodsp") {
+ nodsp = true;
+ continue;
+ }
if (args[argidx] == "-retime") {
retime = true;
continue;
@@ -211,6 +219,22 @@ struct SynthNexusPass : public ScriptPass
log_pop();
}
+ struct DSPRule {
+ int a_maxwidth;
+ int b_maxwidth;
+ int a_minwidth;
+ int b_minwidth;
+ std::string prim;
+ };
+
+ const std::vector<DSPRule> dsp_rules = {
+ {36, 36, 22, 22, "$__NX_MUL36X36"},
+ {36, 18, 22, 10, "$__NX_MUL36X18"},
+ {18, 18, 10, 4, "$__NX_MUL18X18"},
+ {18, 18, 4, 10, "$__NX_MUL18X18"},
+ { 9, 9, 4, 4, "$__NX_MUL9X9"},
+ };
+
void script() override
{
@@ -244,6 +268,18 @@ struct SynthNexusPass : public ScriptPass
run("opt_expr");
run("opt_clean");
+ if (help_mode) {
+ run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
+ run("techmap -map +/nexus/dsp_map.v", "(unless -nodsp)");
+ } else if (!nodsp) {
+ for (const auto &rule : dsp_rules) {
+ run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s",
+ rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim.c_str()));
+ run("chtype -set $mul t:$__soft_mul");
+ }
+ run("techmap -map +/nexus/dsp_map.v");
+ }
+
run("alumacc");
run("opt");
run("memory -nomap");
diff --git a/tests/arch/nexus/mul.ys b/tests/arch/nexus/mul.ys
index 27ea3e04e..65a2fd8c3 100644
--- a/tests/arch/nexus/mul.ys
+++ b/tests/arch/nexus/mul.ys
@@ -1,4 +1,5 @@
read_verilog ../common/mul.v
+chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
hierarchy -top top
proc
@@ -7,22 +8,43 @@ design -save read
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-select -assert-count 7 t:CCU2
-select -assert-max 5 t:WIDEFN9
-select -assert-max 62 t:LUT4
+select -assert-count 1 t:MULT9X9
-select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D
+select -assert-none t:IB t:OB t:VLO t:VHI t:MULT9X9 %% t:* %D
-design -load read
-equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
+hierarchy -top top
+proc
+# equivalence checking is too slow here
+synth_nexus
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:MULT18X18
+select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X18 %% t:* %D
+
+
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
+hierarchy -top top
+proc
+# equivalence checking is too slow here
+synth_nexus
cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:MULT18X36
+select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X36 %% t:* %D
-stat
-select -assert-count 7 t:CCU2
-select -assert-max 12 t:WIDEFN9
-select -assert-max 58 t:LUT4
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
+hierarchy -top top
+proc
+# equivalence checking is too slow here
+synth_nexus
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:MULT36X36
-select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D
+select -assert-none t:IB t:OB t:VLO t:VHI t:MULT36X36 %% t:* %D
diff --git a/tests/arch/nexus/run-test.sh b/tests/arch/nexus/run-test.sh
index bf19b887d..4be4b70ae 100644
--- a/tests/arch/nexus/run-test.sh
+++ b/tests/arch/nexus/run-test.sh
@@ -1,20 +1,4 @@
#!/usr/bin/env bash
-set -e
-{
-echo "all::"
-for x in *.ys; do
- echo "all:: run-$x"
- echo "run-$x:"
- echo " @echo 'Running $x..'"
- echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
-done
-for s in *.sh; do
- if [ "$s" != "run-test.sh" ]; then
- echo "all:: run-$s"
- echo "run-$s:"
- echo " @echo 'Running $s..'"
- echo " @bash $s"
- fi
-done
-} > run-test.mk
-exec ${MAKE:-make} -f run-test.mk
+set -eu
+source ../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-27 02:37:46 +0000