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-rw-r--r--frontends/verilog/verilog_parser.y45
-rw-r--r--misc/py_wrap_generator.py1
-rw-r--r--passes/cmds/setundef.cc118
-rw-r--r--passes/opt/opt_clean.cc2
-rw-r--r--passes/opt/opt_rmdff.cc4
-rw-r--r--passes/sat/fmcombine.cc4
-rw-r--r--passes/sat/sim.cc5
-rw-r--r--passes/techmap/shregmap.cc3
-rw-r--r--techlibs/ecp5/cells_map.v15
-rw-r--r--tests/simple/attrib01_module.v21
-rw-r--r--tests/simple/attrib02_port_decl.v25
-rw-r--r--tests/simple/attrib03_parameter.v28
-rw-r--r--tests/simple/attrib04_net_var.v32
-rw-r--r--tests/simple/attrib05_port_conn.v.DISABLED21
-rw-r--r--tests/simple/attrib06_operator_suffix.v23
-rw-r--r--tests/simple/attrib07_func_call.v.DISABLED21
-rw-r--r--tests/simple/attrib08_mod_inst.v22
-rw-r--r--tests/simple/attrib09_case.v26
-rw-r--r--tests/various/attrib05_port_conn.v21
-rw-r--r--tests/various/attrib05_port_conn.ys2
-rw-r--r--tests/various/attrib07_func_call.v21
-rw-r--r--tests/various/attrib07_func_call.ys2
22 files changed, 411 insertions, 51 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 983445011..2fffc7536 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1532,35 +1532,40 @@ cell_port_list_rules:
cell_port | cell_port_list_rules ',' cell_port;
cell_port:
- /* empty */ {
+ attr {
AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node);
+ free_attr($1);
} |
- expr {
+ attr expr {
AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node);
- node->children.push_back($1);
+ node->children.push_back($2);
+ free_attr($1);
} |
- named_port '(' ')' | // not connected
- named_port '(' expr ')' {
- ($1)->children.push_back($3);
+ attr '.' TOK_ID '(' expr ')' {
+ AstNode *node = new AstNode(AST_ARGUMENT);
+ node->str = *$3;
+ astbuf2->children.push_back(node);
+ node->children.push_back($5);
+ delete $3;
+ free_attr($1);
} |
- named_port {
- // SV implied port
- if (!sv_mode)
- frontend_verilog_yyerror("Implicit .name port connection in port list (%s). This is not supported unless read_verilog is called with -sv!", $1->str.c_str());
- auto id_node = new AstNode(AST_IDENTIFIER);
- id_node->str = ($1)->str;
- ($1)->children.push_back(id_node);
- };
-
-named_port:
- '.' TOK_ID {
+ attr '.' TOK_ID '(' ')' {
AstNode *node = new AstNode(AST_ARGUMENT);
- node->str = *$2;
- delete $2;
+ node->str = *$3;
+ astbuf2->children.push_back(node);
+ delete $3;
+ free_attr($1);
+ } |
+ attr '.' TOK_ID {
+ AstNode *node = new AstNode(AST_ARGUMENT);
+ node->str = *$3;
astbuf2->children.push_back(node);
- $$ = node;
+ node->children.push_back(new AstNode(AST_IDENTIFIER));
+ node->children.back()->str = *$3;
+ delete $3;
+ free_attr($1);
};
always_stmt:
diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py
index 09f934040..9f2c72915 100644
--- a/misc/py_wrap_generator.py
+++ b/misc/py_wrap_generator.py
@@ -2060,7 +2060,6 @@ namespace YOSYS_PYTHON {
Yosys::log_streams.push_back(&std::cout);
Yosys::log_error_stderr = true;
Yosys::yosys_setup();
- Yosys::yosys_banner();
}
}
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index f6949c820..3eedc86b8 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -393,44 +393,112 @@ struct SetundefPass : public Pass {
ffbits.insert(bit);
}
- for (auto wire : module->wires())
+ auto process_initwires = [&]()
{
- if (!wire->attributes.count("\\init"))
- continue;
+ dict<Wire*, int> wire_weights;
- for (auto bit : sigmap(wire))
- ffbits.erase(bit);
+ for (auto wire : initwires)
+ {
+ int weight = 0;
- initwires.insert(wire);
- }
+ for (auto bit : sigmap(wire))
+ weight += ffbits.count(bit) ? +1 : -1;
+
+ wire_weights[wire] = weight;
+ }
+
+ initwires.sort([&](Wire *a, Wire *b) { return wire_weights.at(a) > wire_weights.at(b); });
+
+ for (auto wire : initwires)
+ {
+ Const &initval = wire->attributes["\\init"];
+ initval.bits.resize(GetSize(wire), State::Sx);
+
+ for (int i = 0; i < GetSize(wire); i++) {
+ SigBit bit = sigmap(SigBit(wire, i));
+ if (initval[i] == State::Sx && ffbits.count(bit)) {
+ initval[i] = worker.next_bit();
+ ffbits.erase(bit);
+ }
+ }
+
+ if (initval.is_fully_undef())
+ wire->attributes.erase("\\init");
+ }
+
+ initwires.clear();
+ };
for (int wire_types = 0; wire_types < 2; wire_types++)
- for (auto wire : module->wires())
+ {
+ // prioritize wires that already have an init attribute
+ if (!ffbits.empty())
{
- if (wire->name[0] == (wire_types ? '\\' : '$'))
- next_wire:
- continue;
+ for (auto wire : module->wires())
+ {
+ if (wire->name[0] == (wire_types ? '\\' : '$'))
+ continue;
- for (auto bit : sigmap(wire))
- if (!ffbits.count(bit))
- goto next_wire;
+ if (!wire->attributes.count("\\init"))
+ continue;
- for (auto bit : sigmap(wire))
- ffbits.erase(bit);
+ Const &initval = wire->attributes["\\init"];
+ initval.bits.resize(GetSize(wire), State::Sx);
+
+ if (initval.is_fully_undef()) {
+ wire->attributes.erase("\\init");
+ continue;
+ }
- initwires.insert(wire);
+ for (int i = 0; i < GetSize(wire); i++)
+ if (initval[i] != State::Sx)
+ ffbits.erase(sigmap(SigBit(wire, i)));
+
+ initwires.insert(wire);
+ }
+
+ process_initwires();
}
- for (auto wire : initwires)
- {
- Const &initval = wire->attributes["\\init"];
+ // next consider wires that completely contain bits to be initialized
+ if (!ffbits.empty())
+ {
+ for (auto wire : module->wires())
+ {
+ if (wire->name[0] == (wire_types ? '\\' : '$'))
+ continue;
- for (int i = 0; i < GetSize(wire); i++)
- if (GetSize(initval) <= i)
- initval.bits.push_back(worker.next_bit());
- else if (initval.bits[i] == State::Sx)
- initval.bits[i] = worker.next_bit();
+ for (auto bit : sigmap(wire))
+ if (!ffbits.count(bit))
+ goto next_wire;
+
+ initwires.insert(wire);
+
+ next_wire:
+ continue;
+ }
+
+ process_initwires();
+ }
+
+ // finally use whatever wire we can find.
+ if (!ffbits.empty())
+ {
+ for (auto wire : module->wires())
+ {
+ if (wire->name[0] == (wire_types ? '\\' : '$'))
+ continue;
+
+ for (auto bit : sigmap(wire))
+ if (ffbits.count(bit))
+ initwires.insert(wire);
+ }
+
+ process_initwires();
+ }
}
+
+ log_assert(ffbits.empty());
}
module->rewrite_sigspecs(worker);
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 7011d4602..cfb0f788a 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -106,7 +106,7 @@ void rmunused_module_cells(Module *module, bool verbose)
if (raw_bit.wire == nullptr)
continue;
auto bit = sigmap(raw_bit);
- if (bit.wire == nullptr)
+ if (bit.wire == nullptr && ct_all.cell_known(cell->type))
driver_driver_logs[raw_sigmap(raw_bit)].push_back(stringf("Driver-driver conflict "
"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
log_signal(raw_bit), log_id(cell), log_id(it2.first), log_signal(bit), log_id(module)));
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 2abffa2a9..eeb992a3e 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -292,8 +292,8 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
sig_q = dff->getPort("\\Q");
sig_c = dff->getPort("\\C");
sig_e = dff->getPort("\\E");
- val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
- val_ep = RTLIL::Const(dff->type[7] == 'P', 1);
+ val_cp = RTLIL::Const(dff->type[7] == 'P', 1);
+ val_ep = RTLIL::Const(dff->type[8] == 'P', 1);
}
else if (dff->type == "$ff") {
sig_d = dff->getPort("\\D");
diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc
index f64d99dc2..00c098542 100644
--- a/passes/sat/fmcombine.cc
+++ b/passes/sat/fmcombine.cc
@@ -332,7 +332,7 @@ struct FmcombinePass : public Pass {
gate_cell = module->cell(gate_name);
if (gate_cell == nullptr)
- log_cmd_error("Gold cell %s not found in module %s.\n", log_id(gate_name), log_id(module));
+ log_cmd_error("Gate cell %s not found in module %s.\n", log_id(gate_name), log_id(module));
}
else
{
@@ -351,7 +351,7 @@ struct FmcombinePass : public Pass {
if (!gold_cell->parameters.empty())
log_cmd_error("Gold cell has unresolved instance parameters.\n");
if (!gate_cell->parameters.empty())
- log_cmd_error("Gold cell has unresolved instance parameters.\n");
+ log_cmd_error("Gate cell has unresolved instance parameters.\n");
FmcombineWorker worker(design, gold_cell->type, opts);
worker.generate();
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 53e248adf..4c3022c70 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -88,6 +88,8 @@ struct SimInstance
SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
shared(shared), module(module), instance(instance), parent(parent), sigmap(module)
{
+ log_assert(module);
+
if (parent) {
log_assert(parent->children.count(instance) == 0);
parent->children[instance] = this;
@@ -848,6 +850,9 @@ struct SimPass : public Pass {
if (design->full_selection()) {
top_mod = design->top_module();
+
+ if (!top_mod)
+ log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
} else {
auto mods = design->selected_whole_modules();
if (GetSize(mods) != 1)
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 75eedfbcc..21dfe9619 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -606,6 +606,9 @@ struct ShregmapPass : public Pass {
log(" -tech greenpak4\n");
log(" map to greenpak4 shift registers.\n");
log("\n");
+ log(" -tech xilinx\n");
+ log(" map to xilinx dynamic-length shift registers.\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 6ab4b69f2..f6c71a03d 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,6 +47,21 @@ module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"
module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+// Diamond I/O buffers
+module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
+module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBCO (input I, output OT, OC); OLVDS _TECHMAP_REPLACE_ (.A(I), .Z(OT), .ZN(OC)); endmodule
+module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
+module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
+
// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v
new file mode 100644
index 000000000..adef34f5b
--- /dev/null
+++ b/tests/simple/attrib01_module.v
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v
new file mode 100644
index 000000000..3505e7265
--- /dev/null
+++ b/tests/simple/attrib02_port_decl.v
@@ -0,0 +1,25 @@
+module bar(clk, rst, inp, out);
+ (* this_is_clock = 1 *)
+ input wire clk;
+ (* this_is_reset = 1 *)
+ input wire rst;
+ input wire inp;
+ (* an_output_register = 1*)
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ (* this_is_the_master_clock *)
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v
new file mode 100644
index 000000000..562d225cd
--- /dev/null
+++ b/tests/simple/attrib03_parameter.v
@@ -0,0 +1,28 @@
+module bar(clk, rst, inp, out);
+
+ (* bus_width *)
+ parameter WIDTH = 2;
+
+ (* an_attribute_on_localparam = 55 *)
+ localparam INCREMENT = 5;
+
+ input wire clk;
+ input wire rst;
+ input wire [WIDTH-1:0] inp;
+ output reg [WIDTH-1:0] out;
+
+ always @(posedge clk)
+ if (rst) out <= 0;
+ else out <= inp + INCREMENT;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp;
+ output wire [7:0] out;
+
+ bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v
new file mode 100644
index 000000000..8b5523406
--- /dev/null
+++ b/tests/simple/attrib04_net_var.v
@@ -0,0 +1,32 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ (* this_is_a_prescaler *)
+ reg [7:0] counter;
+
+ (* temp_wire *)
+ wire out_val;
+
+ always @(posedge clk)
+ counter <= counter + 1;
+
+ assign out_val = inp ^ counter[4];
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= out_val;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED
new file mode 100644
index 000000000..e20e66319
--- /dev/null
+++ b/tests/simple/attrib05_port_conn.v.DISABLED
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+endmodule
+
diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v
new file mode 100644
index 000000000..e21173c58
--- /dev/null
+++ b/tests/simple/attrib06_operator_suffix.v
@@ -0,0 +1,23 @@
+module bar(clk, rst, inp_a, inp_b, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp_a;
+ input wire [7:0] inp_b;
+ output reg [7:0] out;
+
+ always @(posedge clk)
+ if (rst) out <= 0;
+ else out <= inp_a + (* ripple_adder *) inp_b;
+
+endmodule
+
+module foo(clk, rst, inp_a, inp_b, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp_a;
+ input wire [7:0] inp_b;
+ output wire [7:0] out;
+
+ bar bar_instance (clk, rst, inp_a, inp_b, out);
+endmodule
+
diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED
new file mode 100644
index 000000000..f55ef2316
--- /dev/null
+++ b/tests/simple/attrib07_func_call.v.DISABLED
@@ -0,0 +1,21 @@
+function [7:0] do_add;
+ input [7:0] inp_a;
+ input [7:0] inp_b;
+
+ do_add = inp_a + inp_b;
+
+endfunction
+
+module foo(clk, rst, inp_a, inp_b, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp_a;
+ input wire [7:0] inp_b;
+ output wire [7:0] out;
+
+ always @(posedge clk)
+ if (rst) out <= 0;
+ else out <= do_add (* combinational_adder *) (inp_a, inp_b);
+
+endmodule
+
diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v
new file mode 100644
index 000000000..c5a32234e
--- /dev/null
+++ b/tests/simple/attrib08_mod_inst.v
@@ -0,0 +1,22 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ (* my_module_instance = 99 *)
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v
new file mode 100644
index 000000000..8551bf9d0
--- /dev/null
+++ b/tests/simple/attrib09_case.v
@@ -0,0 +1,26 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire [1:0] inp;
+ output reg [1:0] out;
+
+ always @(inp)
+ (* full_case, parallel_case *)
+ case(inp)
+ 2'd0: out <= 2'd3;
+ 2'd1: out <= 2'd2;
+ 2'd2: out <= 2'd1;
+ 2'd3: out <= 2'd0;
+ endcase
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire [1:0] inp;
+ output wire [1:0] out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/various/attrib05_port_conn.v b/tests/various/attrib05_port_conn.v
new file mode 100644
index 000000000..e20e66319
--- /dev/null
+++ b/tests/various/attrib05_port_conn.v
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+endmodule
+
diff --git a/tests/various/attrib05_port_conn.ys b/tests/various/attrib05_port_conn.ys
new file mode 100644
index 000000000..27a016733
--- /dev/null
+++ b/tests/various/attrib05_port_conn.ys
@@ -0,0 +1,2 @@
+# Read and parse Verilog file
+read_verilog attrib05_port_conn.v
diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v
new file mode 100644
index 000000000..f55ef2316
--- /dev/null
+++ b/tests/various/attrib07_func_call.v
@@ -0,0 +1,21 @@
+function [7:0] do_add;
+ input [7:0] inp_a;
+ input [7:0] inp_b;
+
+ do_add = inp_a + inp_b;
+
+endfunction
+
+module foo(clk, rst, inp_a, inp_b, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp_a;
+ input wire [7:0] inp_b;
+ output wire [7:0] out;
+
+ always @(posedge clk)
+ if (rst) out <= 0;
+ else out <= do_add (* combinational_adder *) (inp_a, inp_b);
+
+endmodule
+
diff --git a/tests/various/attrib07_func_call.ys b/tests/various/attrib07_func_call.ys
new file mode 100644
index 000000000..774827651
--- /dev/null
+++ b/tests/various/attrib07_func_call.ys
@@ -0,0 +1,2 @@
+# Read and parse Verilog file
+read_verilog attrib07_func_call.v
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-27 05:38:53 +0000