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-rw-r--r--frontends/verilog/Makefile.inc2
-rw-r--r--frontends/verilog/verilog_parser.y138
-rw-r--r--passes/opt/opt_merge.cc4
-rw-r--r--techlibs/achronix/synth_achronix.cc2
-rw-r--r--tests/various/integer_range_bad_syntax.ys6
-rw-r--r--tests/various/integer_real_bad_syntax.ys6
-rw-r--r--tests/various/logic_param_simple.ys9
-rw-r--r--tests/various/signed.ys28
8 files changed, 118 insertions, 77 deletions
diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index d5d5edd3d..2c923f0b7 100644
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -6,7 +6,7 @@ GENFILES += frontends/verilog/verilog_lexer.cc
frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
$(Q) mkdir -p $(dir $@)
- $(P) $(BISON) -Werror=conflicts-sr,error=conflicts-rr -o $@ -d -r all -b frontends/verilog/verilog_parser $<
+ $(P) $(BISON) -Wall -Werror -o $@ -d -r all -b frontends/verilog/verilog_parser $<
frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 0fdf2b516..63f0341d9 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -299,14 +299,14 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%left '+' '-'
%left '*' '/' '%'
%left OP_POW
-%left OP_CAST
-%right UNARY_OPS
+%precedence OP_CAST
+%precedence UNARY_OPS
%define parse.error verbose
%define parse.lac full
-%nonassoc FAKE_THEN
-%nonassoc TOK_ELSE
+%precedence FAKE_THEN
+%precedence TOK_ELSE
%debug
%locations
@@ -333,7 +333,7 @@ design:
typedef_decl design |
package design |
interface design |
- /* empty */;
+ %empty;
attr:
{
@@ -355,7 +355,7 @@ attr_opt:
attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
SET_RULE_LOC(@$, @2, @$);
}|
- /* empty */;
+ %empty;
defattr:
DEFATTR_BEGIN {
@@ -376,7 +376,7 @@ defattr:
} DEFATTR_END;
opt_attr_list:
- attr_list | /* empty */;
+ attr_list | %empty;
attr_list:
attr_assign |
@@ -449,13 +449,13 @@ module:
};
module_para_opt:
- '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
+ '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | %empty;
module_para_list:
single_module_para | module_para_list ',' single_module_para;
single_module_para:
- /* empty */ |
+ %empty |
attr TOK_PARAMETER {
if (astbuf1) delete astbuf1;
astbuf1 = new AstNode(AST_PARAMETER);
@@ -471,13 +471,13 @@ single_module_para:
single_param_decl;
module_args_opt:
- '(' ')' | /* empty */ | '(' module_args optional_comma ')';
+ '(' ')' | %empty | '(' module_args optional_comma ')';
module_args:
module_arg | module_args ',' module_arg;
optional_comma:
- ',' | /* empty */;
+ ',' | %empty;
module_arg_opt_assignment:
'=' expr {
@@ -497,7 +497,7 @@ module_arg_opt_assignment:
} else
frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
} |
- /* empty */;
+ %empty;
module_arg:
TOK_ID {
@@ -565,15 +565,10 @@ package:
};
package_body:
- package_body package_body_stmt
- | // optional
- ;
+ package_body package_body_stmt | %empty;
package_body_stmt:
- typedef_decl
- | localparam_decl
- | param_decl
- ;
+ typedef_decl | localparam_decl | param_decl;
interface:
TOK_INTERFACE {
@@ -599,7 +594,7 @@ interface:
};
interface_body:
- interface_body interface_body_stmt |;
+ interface_body interface_body_stmt | %empty;
interface_body_stmt:
param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
@@ -613,7 +608,7 @@ non_opt_delay:
'#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
delay:
- non_opt_delay | /* empty */;
+ non_opt_delay | %empty;
wire_type:
{
@@ -725,7 +720,7 @@ range:
non_opt_range {
$$ = $1;
} |
- /* empty */ {
+ %empty {
$$ = NULL;
};
@@ -742,7 +737,8 @@ module_body:
module_body module_body_stmt |
/* the following line makes the generate..endgenrate keywords optional */
module_body gen_stmt |
- /* empty */;
+ module_body ';' |
+ %empty;
module_body_stmt:
task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
@@ -842,28 +838,28 @@ dpi_function_arg:
opt_dpi_function_args:
'(' dpi_function_args ')' |
- /* empty */;
+ %empty;
dpi_function_args:
dpi_function_args ',' dpi_function_arg |
dpi_function_args ',' |
dpi_function_arg |
- /* empty */;
+ %empty;
opt_automatic:
TOK_AUTOMATIC |
- /* empty */;
+ %empty;
opt_signed:
TOK_SIGNED {
$$ = true;
} |
- /* empty */ {
+ %empty {
$$ = false;
};
task_func_args_opt:
- '(' ')' | /* empty */ | '(' {
+ '(' ')' | %empty | '(' {
albuf = nullptr;
astbuf1 = nullptr;
astbuf2 = nullptr;
@@ -904,7 +900,7 @@ task_func_port:
task_func_body:
task_func_body behavioral_stmt |
- /* empty */;
+ %empty;
/*************************** specify parser ***************************/
@@ -913,7 +909,7 @@ specify_block:
specify_item_list:
specify_item specify_item_list |
- /* empty */;
+ %empty;
specify_item:
specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
@@ -1075,7 +1071,7 @@ specify_opt_triple:
',' specify_triple {
$$ = $2;
} |
- /* empty */ {
+ %empty {
$$ = nullptr;
};
@@ -1083,7 +1079,7 @@ specify_if:
TOK_IF '(' expr ')' {
$$ = $3;
} |
- /* empty */ {
+ %empty {
$$ = nullptr;
};
@@ -1091,7 +1087,7 @@ specify_condition:
TOK_SPECIFY_AND expr {
$$ = $2;
} |
- /* empty */ {
+ %empty {
$$ = nullptr;
};
@@ -1124,7 +1120,7 @@ specify_target:
specify_edge:
TOK_POSEDGE { $$ = 'p'; } |
TOK_NEGEDGE { $$ = 'n'; } |
- { $$ = 0; };
+ %empty { $$ = 0; };
specify_rise_fall:
specify_triple {
@@ -1231,7 +1227,7 @@ specparam_assignment:
ignspec_id '=' ignspec_expr ;
ignspec_opt_cond:
- TOK_IF '(' ignspec_expr ')' | /* empty */;
+ TOK_IF '(' ignspec_expr ')' | %empty;
path_declaration :
simple_path_declaration ';'
@@ -1282,9 +1278,7 @@ list_of_path_outputs :
list_of_path_outputs ',' specify_output_terminal_descriptor ;
opt_polarity_operator :
- '+'
- | '-'
- | ;
+ '+' | '-' | %empty;
// Good enough for the time being
specify_input_terminal_descriptor :
@@ -1331,36 +1325,36 @@ ignspec_id:
param_signed:
TOK_SIGNED {
astbuf1->is_signed = true;
- } | /* empty */;
+ } | TOK_UNSIGNED {
+ astbuf1->is_signed = false;
+ } | %empty;
param_integer:
TOK_INTEGER {
- if (astbuf1->children.size() != 1)
- frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
astbuf1->children.push_back(new AstNode(AST_RANGE));
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
astbuf1->is_signed = true;
- } | /* empty */;
+ };
param_real:
TOK_REAL {
- if (astbuf1->children.size() != 1)
- frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
astbuf1->children.push_back(new AstNode(AST_REALVALUE));
- } | /* empty */;
+ };
param_range:
range {
if ($1 != NULL) {
- if (astbuf1->children.size() != 1)
- frontend_verilog_yyerror("integer/real parameters should not have a range.");
astbuf1->children.push_back($1);
}
};
+param_integer_type: param_integer param_signed;
+param_range_type: type_vec param_signed param_range;
+param_implicit_type: param_signed param_range;
+
param_type:
- param_signed param_integer param_real param_range |
+ param_integer_type | param_real | param_range_type | param_implicit_type |
hierarchical_type_id {
astbuf1->is_custom_type = true;
astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
@@ -1450,7 +1444,7 @@ enum_type: TOK_ENUM {
enum_base_type: type_atom type_signing
| type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
- | /* nothing */ { astbuf1->is_reg = true; addRange(astbuf1); }
+ | %empty { astbuf1->is_reg = true; addRange(astbuf1); }
;
type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed
@@ -1466,7 +1460,7 @@ type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned
type_signing:
TOK_SIGNED { astbuf1->is_signed = true; }
| TOK_UNSIGNED { astbuf1->is_signed = false; }
- | // optional
+ | %empty
;
enum_name_list: enum_name_decl
@@ -1490,7 +1484,7 @@ enum_name_decl:
opt_enum_init:
'=' basic_expr { $$ = $2; } // TODO: restrict this
- | /* optional */ { $$ = NULL; }
+ | %empty { $$ = NULL; }
;
enum_var_list:
@@ -1531,14 +1525,14 @@ struct_union:
struct_body: opt_packed '{' struct_member_list '}'
;
-opt_packed: TOK_PACKED opt_signed_struct
- | { frontend_verilog_yyerror("Only PACKED supported at this time"); }
- ;
+opt_packed:
+ TOK_PACKED opt_signed_struct |
+ %empty { frontend_verilog_yyerror("Only PACKED supported at this time"); };
opt_signed_struct:
TOK_SIGNED { astbuf2->is_signed = true; }
| TOK_UNSIGNED { astbuf2->is_signed = false; }
- | // default is unsigned
+ | %empty // default is unsigned
;
struct_member_list: struct_member
@@ -1645,7 +1639,7 @@ wire_decl:
} opt_supply_wires ';';
opt_supply_wires:
- /* empty */ |
+ %empty |
opt_supply_wires ',' TOK_ID {
AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
@@ -1876,13 +1870,13 @@ single_prim:
}
cell_parameter_list_opt:
- '#' '(' cell_parameter_list ')' | /* empty */;
+ '#' '(' cell_parameter_list ')' | %empty;
cell_parameter_list:
cell_parameter | cell_parameter_list ',' cell_parameter;
cell_parameter:
- /* empty */ |
+ %empty |
expr {
AstNode *node = new AstNode(AST_PARASET);
astbuf1->children.push_back(node);
@@ -2040,7 +2034,7 @@ always_cond:
'@' ATTR_BEGIN ')' |
'@' '(' ATTR_END |
'@' '*' |
- /* empty */;
+ %empty;
always_events:
always_event |
@@ -2070,7 +2064,7 @@ opt_label:
':' TOK_ID {
$$ = $2;
} |
- /* empty */ {
+ %empty {
$$ = NULL;
};
@@ -2078,7 +2072,7 @@ opt_sva_label:
TOK_SVA_LABEL ':' {
$$ = $1;
} |
- /* empty */ {
+ %empty {
$$ = NULL;
};
@@ -2089,7 +2083,7 @@ opt_property:
TOK_FINAL {
$$ = false;
} |
- /* empty */ {
+ %empty {
$$ = false;
};
@@ -2500,7 +2494,7 @@ behavioral_stmt:
};
unique_case_attr:
- /* empty */ {
+ %empty {
$$ = false;
} |
TOK_PRIORITY case_attr {
@@ -2536,11 +2530,11 @@ opt_synopsys_attr:
if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
} |
- /* empty */;
+ %empty;
behavioral_stmt_list:
behavioral_stmt_list behavioral_stmt |
- /* empty */;
+ %empty;
optional_else:
TOK_ELSE {
@@ -2554,11 +2548,11 @@ optional_else:
} behavioral_stmt {
SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
} |
- /* empty */ %prec FAKE_THEN;
+ %empty %prec FAKE_THEN;
case_body:
case_body case_item |
- /* empty */;
+ %empty;
case_item:
{
@@ -2581,7 +2575,7 @@ case_item:
gen_case_body:
gen_case_body gen_case_item |
- /* empty */;
+ %empty;
gen_case_item:
{
@@ -2665,11 +2659,11 @@ lvalue_concat_list:
opt_arg_list:
'(' arg_list optional_comma ')' |
- /* empty */;
+ %empty;
arg_list:
arg_list2 |
- /* empty */;
+ %empty;
arg_list2:
single_arg |
@@ -2682,7 +2676,7 @@ single_arg:
module_gen_body:
module_gen_body gen_stmt_or_module_body_stmt |
- /* empty */;
+ %empty;
gen_stmt_or_module_body_stmt:
gen_stmt | module_body_stmt |
@@ -2761,7 +2755,7 @@ gen_stmt_block:
};
opt_gen_else:
- TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN;
+ TOK_ELSE gen_stmt_block | %empty %prec FAKE_THEN;
expr:
basic_expr {
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index f03faa9cf..9086943dc 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -173,9 +173,7 @@ struct OptMergeWorker
for (const auto &it : cell1->connections_) {
if (cell1->output(it.first)) {
- if (it.first == ID::Q && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
- cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
- cell1->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
+ if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell1->type)) {
// For the 'Q' output of state elements,
// use the (* init *) attribute value
auto &sig1 = conn1[it.first];
diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index ddd9822b9..b203828d2 100644
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -144,12 +144,12 @@ struct SynthAchronixPass : public ScriptPass {
run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map");
run("opt -undriven -fine");
- run("dff2dffe -direct-match $_DFF_*");
run("opt -fine");
run("techmap -map +/techmap.v");
run("opt -full");
run("clean -purge");
run("setundef -undriven -zero");
+ run("dfflegalize -cell $_DFF_P_ x");
if (retime || help_mode)
run("abc -markgroups -dff -D 1", "(only if -retime)");
}
diff --git a/tests/various/integer_range_bad_syntax.ys b/tests/various/integer_range_bad_syntax.ys
new file mode 100644
index 000000000..4f427211f
--- /dev/null
+++ b/tests/various/integer_range_bad_syntax.ys
@@ -0,0 +1,6 @@
+logger -expect error "syntax error, unexpected" 1
+read_verilog -sv <<EOT
+module test_integer_range();
+parameter integer [31:0] a = 0;
+endmodule
+EOT
diff --git a/tests/various/integer_real_bad_syntax.ys b/tests/various/integer_real_bad_syntax.ys
new file mode 100644
index 000000000..942d8de77
--- /dev/null
+++ b/tests/various/integer_real_bad_syntax.ys
@@ -0,0 +1,6 @@
+logger -expect error "syntax error, unexpected TOK_REAL" 1
+read_verilog -sv <<EOT
+module test_integer_real();
+parameter integer real a = 0;
+endmodule
+EOT
diff --git a/tests/various/logic_param_simple.ys b/tests/various/logic_param_simple.ys
new file mode 100644
index 000000000..968564080
--- /dev/null
+++ b/tests/various/logic_param_simple.ys
@@ -0,0 +1,9 @@
+read_verilog -sv <<EOT
+module test_logic_param();
+parameter logic a = 0;
+parameter logic [31:0] e = 0;
+parameter logic signed b = 0;
+parameter logic unsigned c = 0;
+parameter logic unsigned [31:0] d = 0;
+endmodule
+EOT
diff --git a/tests/various/signed.ys b/tests/various/signed.ys
new file mode 100644
index 000000000..2319a5da1
--- /dev/null
+++ b/tests/various/signed.ys
@@ -0,0 +1,28 @@
+# SV LRM A2.2.1
+
+read_verilog -sv <<EOT
+module test_signed();
+parameter integer signed a = 0;
+parameter integer unsigned b = 0;
+
+endmodule
+EOT
+
+design -reset
+read_verilog -sv <<EOT
+module test_signed();
+parameter logic signed [7:0] a = 0;
+parameter logic unsigned [7:0] b = 0;
+
+endmodule
+EOT
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_INTEGER" 1
+read_verilog -sv <<EOT
+module test_signed();
+parameter signed integer a = 0;
+parameter unsigned integer b = 0;
+
+endmodule
+EOT
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-04 06:51:55 +0000