diff options
| -rw-r--r-- | CHANGELOG | 2 | ||||
| -rw-r--r-- | manual/APPNOTE_010_Verilog_to_BLIF.tex | 6 | ||||
| -rw-r--r-- | manual/APPNOTE_011_Design_Investigation.tex | 2 | ||||
| -rw-r--r-- | manual/literature.bib | 326 | ||||
| -rw-r--r-- | manual/weblinks.bib | 268 | ||||
| -rw-r--r-- | passes/cmds/scc.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/abc.cc | 2 | ||||
| -rw-r--r-- | tests/asicworld/code_hdl_models_arbiter.v | 246 | ||||
| -rw-r--r-- | tests/asicworld/code_hdl_models_t_gate_switch.v | 22 | ||||
| -rw-r--r-- | tests/asicworld/code_hdl_models_up_counter.v | 2 | ||||
| -rw-r--r-- | tests/asicworld/code_verilog_tutorial_counter.v | 38 | ||||
| -rw-r--r-- | tests/asicworld/code_verilog_tutorial_counter_tb.v | 226 |
12 files changed, 571 insertions, 571 deletions
@@ -83,7 +83,7 @@ Yosys 0.3.0 .. Yosys 0.4 - There is now a "synth" command with a recommended default script - Many improvements in synthesis of arithmetic functions to gates - Multiplieres and adders with many operands are using carry-save adder trees - - Remaining adders are now implemented using Brent–Kung carry look-ahead adders + - Remaining adders are now implemented using Brent-Kung carry look-ahead adders - Various new high-level optimizations on RTL netlist - Various improvements in FSM optimization - Updated ABC to hg 5b5af75f1dda (from 2014-11-07) diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex index 3e36fa386..0ecdf6194 100644 --- a/manual/APPNOTE_010_Verilog_to_BLIF.tex +++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex @@ -100,7 +100,7 @@ regression testing Yosys. \section{Getting Started} -We start our tour with the Navré processor from yosys-bigsim. The Navré +We start our tour with the Navr\'e processor from yosys-bigsim. The Navr\'e processor \cite{navre} is an Open Source AVR clone. It is a single module ({\tt softusb\_navre}) in a single design file ({\tt softusb\_navre.v}). It also is using only features that map nicely to the BLIF format, for example it only @@ -226,7 +226,7 @@ further processed using custom commands. But in this case we don't want that. \medskip So now we have the final synthesis script for generating a BLIF file -for the Navré CPU: +for the Navr\'e CPU: \begin{figure}[H] \begin{lstlisting}[language=sh] @@ -445,7 +445,7 @@ yosys-bigsim, a collection of real-world Verilog designs for regression testing \url{https://github.com/cliffordwolf/yosys-bigsim} \bibitem{navre} -Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\ +Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\ \url{http://opencores.org/project,navre} \bibitem{amber} diff --git a/manual/APPNOTE_011_Design_Investigation.tex b/manual/APPNOTE_011_Design_Investigation.tex index b9a8237f4..02fb99d36 100644 --- a/manual/APPNOTE_011_Design_Investigation.tex +++ b/manual/APPNOTE_011_Design_Investigation.tex @@ -1061,7 +1061,7 @@ MiniSat: a minimalistic open-source SAT solver. \url{http://minisat.se/} \bibitem{tip} -Niklas Een and Niklas Sörensson (2003). +Niklas Een and Niklas S\"orensson (2003). Temporal Induction by Incremental SAT Solving. \url{http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.4.8161} diff --git a/manual/literature.bib b/manual/literature.bib index 91bc1f382..372e882ac 100644 --- a/manual/literature.bib +++ b/manual/literature.bib @@ -1,163 +1,163 @@ -
-@inproceedings{intersynth,
- title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic},
- author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm},
- booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages},
- pages={194--201},
- year={2012}
-}
-
-@incollection{intersynthFdlBookChapter,
- title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures},
- author={Johann Glaser and Clifford Wolf},
- booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12},
- editor={Jan Haase},
- publisher={Springer},
- year={2013},
- note={to appear}
-}
-
-@unpublished{BACC,
- author = {Clifford Wolf},
- title = {Design and Implementation of the Yosys Open SYnthesis Suite},
- note = {Bachelor Thesis, Vienna University of Technology},
- year = {2013}
-}
-
-@unpublished{VerilogFossEval,
- author = {Clifford Wolf},
- title = {Evaluation of Open Source Verilog Synthesis Tools for Feature-Completeness and Extensibility},
- note = {Unpublished Student Research Paper, Vienna University of Technology},
- year = {2012}
-}
-
-@article{ABEL,
- title={A High-Level Design Language for Programmable Logic Devices},
- author={Kyu Y. Lee and Michael Holley and Mary Bailey and Walter Bright},
- journal={VLSI Design (Manhasset NY: CPM Publications)},
- year={June 1985},
- pages={50-62}
-}
-
-@MISC{Cheng93vl2mv:a,
- author = {S-T Cheng and G York and R K Brayton},
- title = {VL2MV: A Compiler from Verilog to BLIF-MV},
- year = {1993}
-}
-
-@MISC{Odin,
- author = {Peter Jamieson and Jonathan Rose},
- title = {A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS},
- year = {2005}
-}
-
-@inproceedings{vtr2012,
- title={The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing},
- author={Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
- booktitle={Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
- pages={77--86},
- year={2012},
- organization={ACM}
-}
-
-@MISC{LogicSynthesis,
- author = {G D Hachtel and F Somenzi},
- title = {Logic Synthesis and Verification Algorithms},
- year = {1996}
-}
-
-@ARTICLE{Verilog2005,
- journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},
- title={IEEE Standard for Verilog Hardware Description Language},
- year={2006},
- doi={10.1109/IEEESTD.2006.99495}
-}
-
-@ARTICLE{VerilogSynth,
- journal={IEEE Std 1364.1-2002},
- title={IEEE Standard for Verilog Register Transfer Level Synthesis},
- year={2002},
- doi={10.1109/IEEESTD.2002.94220}
-}
-
-@ARTICLE{VHDL,
- journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, title={IEEE Standard VHDL Language Reference Manual},
- year={2009},
- month={26},
- doi={10.1109/IEEESTD.2009.4772740}
-}
-
-@ARTICLE{VHDLSynth,
- journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis},
- year={2004},
- doi={10.1109/IEEESTD.2004.94802}
-}
-
-@ARTICLE{IP-XACT,
-journal={IEEE Std 1685-2009}, title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows},
-year={2010},
-pages={C1-360},
-keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema},
-doi={10.1109/IEEESTD.2010.5417309},}
-
-@book{Dragonbook,
-author = {Aho, Alfred V. and Sethi, Ravi and Ullman, Jeffrey D.},
-title = {Compilers: principles, techniques, and tools},
-year = {1986},
-isbn = {0-201-10088-6},
-publisher = {Addison-Wesley Longman Publishing Co., Inc.},
-address = {Boston, MA, USA},
-}
-
-@INPROCEEDINGS{Cummings00,
-author = {Clifford E. Cummings and Sunburst Design Inc},
-title = {Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill},
-booktitle = {SNUG (Synopsys Users Group) 2000 User Papers, section-MC1 (1 st paper},
-year = {2000}
-}
-
-@ARTICLE{MURPHY,
- author={D. L. Klipstein},
- journal={Cahners Publishing Co., EEE Magazine, Vol. 15, No. 8},
- title={The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects},
- year={August 1967}
-}
-
-@INPROCEEDINGS{fsmextract,
-author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren},
-booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
-title={A highly efficient method for extracting FSMs from flattened gate-level netlist},
-year={2010},
-pages={2610-2613},
-keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing},
-doi={10.1109/ISCAS.2010.5537093},}
-
-@ARTICLE{MultiLevelLogicSynth,
-author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.},
-journal={Proceedings of the IEEE},
-title={Multilevel logic synthesis},
-year={1990},
-volume={78},
-number={2},
-pages={264-300},
-keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon},
-doi={10.1109/5.52213},
-ISSN={0018-9219},}
-
-@article{UllmannSubgraphIsomorphism,
- author = {Ullmann, J. R.},
- title = {An Algorithm for Subgraph Isomorphism},
- journal = {J. ACM},
- issue_date = {Jan. 1976},
- volume = {23},
- number = {1},
- month = jan,
- year = {1976},
- issn = {0004-5411},
- pages = {31--42},
- numpages = {12},
- doi = {10.1145/321921.321925},
- acmid = {321925},
- publisher = {ACM},
- address = {New York, NY, USA},
-}
+ +@inproceedings{intersynth, + title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic}, + author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm}, + booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages}, + pages={194--201}, + year={2012} +} + +@incollection{intersynthFdlBookChapter, + title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures}, + author={Johann Glaser and Clifford Wolf}, + booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12}, + editor={Jan Haase}, + publisher={Springer}, + year={2013}, + note={to appear} +} + +@unpublished{BACC, + author = {Clifford Wolf}, + title = {Design and Implementation of the Yosys Open SYnthesis Suite}, + note = {Bachelor Thesis, Vienna University of Technology}, + year = {2013} +} + +@unpublished{VerilogFossEval, + author = {Clifford Wolf}, + title = {Evaluation of Open Source Verilog Synthesis Tools for Feature-Completeness and Extensibility}, + note = {Unpublished Student Research Paper, Vienna University of Technology}, + year = {2012} +} + +@article{ABEL, + title={A High-Level Design Language for Programmable Logic Devices}, + author={Kyu Y. Lee and Michael Holley and Mary Bailey and Walter Bright}, + journal={VLSI Design (Manhasset NY: CPM Publications)}, + year={June 1985}, + pages={50-62} +} + +@MISC{Cheng93vl2mv:a, + author = {S-T Cheng and G York and R K Brayton}, + title = {VL2MV: A Compiler from Verilog to BLIF-MV}, + year = {1993} +} + +@MISC{Odin, + author = {Peter Jamieson and Jonathan Rose}, + title = {A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS}, + year = {2005} +} + +@inproceedings{vtr2012, + title={The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing}, + author={Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson}, + booktitle={Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays}, + pages={77--86}, + year={2012}, + organization={ACM} +} + +@MISC{LogicSynthesis, + author = {G D Hachtel and F Somenzi}, + title = {Logic Synthesis and Verification Algorithms}, + year = {1996} +} + +@ARTICLE{Verilog2005, + journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)}, + title={IEEE Standard for Verilog Hardware Description Language}, + year={2006}, + doi={10.1109/IEEESTD.2006.99495} +} + +@ARTICLE{VerilogSynth, + journal={IEEE Std 1364.1-2002}, + title={IEEE Standard for Verilog Register Transfer Level Synthesis}, + year={2002}, + doi={10.1109/IEEESTD.2002.94220} +} + +@ARTICLE{VHDL, + journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, title={IEEE Standard VHDL Language Reference Manual}, + year={2009}, + month={26}, + doi={10.1109/IEEESTD.2009.4772740} +} + +@ARTICLE{VHDLSynth, + journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis}, + year={2004}, + doi={10.1109/IEEESTD.2004.94802} +} + +@ARTICLE{IP-XACT, +journal={IEEE Std 1685-2009}, title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, +year={2010}, +pages={C1-360}, +keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, +doi={10.1109/IEEESTD.2010.5417309},} + +@book{Dragonbook, +author = {Aho, Alfred V. and Sethi, Ravi and Ullman, Jeffrey D.}, +title = {Compilers: principles, techniques, and tools}, +year = {1986}, +isbn = {0-201-10088-6}, +publisher = {Addison-Wesley Longman Publishing Co., Inc.}, +address = {Boston, MA, USA}, +} + +@INPROCEEDINGS{Cummings00, +author = {Clifford E. Cummings and Sunburst Design Inc}, +title = {Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill}, +booktitle = {SNUG (Synopsys Users Group) 2000 User Papers, section-MC1 (1 st paper}, +year = {2000} +} + +@ARTICLE{MURPHY, + author={D. L. Klipstein}, + journal={Cahners Publishing Co., EEE Magazine, Vol. 15, No. 8}, + title={The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects}, + year={August 1967} +} + +@INPROCEEDINGS{fsmextract, +author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, +booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, +title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, +year={2010}, +pages={2610-2613}, +keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, +doi={10.1109/ISCAS.2010.5537093},} + +@ARTICLE{MultiLevelLogicSynth, +author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, +journal={Proceedings of the IEEE}, +title={Multilevel logic synthesis}, +year={1990}, +volume={78}, +number={2}, +pages={264-300}, +keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, +doi={10.1109/5.52213}, +ISSN={0018-9219},} + +@article{UllmannSubgraphIsomorphism, + author = {Ullmann, J. R.}, + title = {An Algorithm for Subgraph Isomorphism}, + journal = {J. ACM}, + issue_date = {Jan. 1976}, + volume = {23}, + number = {1}, + month = jan, + year = {1976}, + issn = {0004-5411}, + pages = {31--42}, + numpages = {12}, + doi = {10.1145/321921.321925}, + acmid = {321925}, + publisher = {ACM}, + address = {New York, NY, USA}, +} diff --git a/manual/weblinks.bib b/manual/weblinks.bib index 5215a6ca3..d5f83315d 100644 --- a/manual/weblinks.bib +++ b/manual/weblinks.bib @@ -1,134 +1,134 @@ -
-@misc{YosysGit,
- author = {Clifford Wolf},
- title = {{Yosys Open SYnthesis Suite (YOSYS)}},
- note = {\url{http://github.com/cliffordwolf/yosys}}
-}
-
-@misc{YosysTestsGit,
- author = {Clifford Wolf},
- title = {{Yosys Test Bench}},
- note = {\url{http://github.com/cliffordwolf/yosys-tests}}
-}
-
-@misc{VlogHammer,
- author = {Clifford Wolf},
- title = {{VlogHammer Verilog Synthesis Regression Tests}},
- note = {\url{http://github.com/cliffordwolf/VlogHammer}}
-}
-
-@misc{Icarus,
- author = {Stephen Williams},
- title = {{Icarus Verilog}},
- note = {Version 0.8.7, \url{http://iverilog.icarus.com/}}
-}
-
-@misc{VTR,
- author= {Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
- title = {{The Verilog-to-Routing (VTR) Project for FPGAs}},
- note = {Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}}
-}
-
-@misc{HANA,
- author = {Parvez Ahmad},
- title = {{HDL Analyzer and Netlist Architect (HANA)}},
- note = {Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}}
-}
-
-@misc{MVSIS,
- author = {MVSIS group at Berkeley studies logic synthesis and verification for VLSI design},
- title = {{MVSIS: Logic Synthesis and Verification}},
- note = {Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}}
-}
-
-@misc{VIS,
- author = {{The VIS group}},
- title = {{VIS: A system for Verification and Synthesis}},
- note = {Version 2.4, \url{http://vlsi.colorado.edu/~vis/}}
-}
-
-@misc{ABC,
- author = {{Berkeley Logic Synthesis and Verification Group}},
- title = {{ABC: A System for Sequential Synthesis and Verification}},
- note = {HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}}
-}
-
-@misc{AIGER,
- author = {{Armin Biere, Johannes Kepler University Linz, Austria}},
- title = {{AIGER}},
- note = {\url{http://fmv.jku.at/aiger/}}
-}
-
-@misc{XilinxWebPACK,
- author = {{Xilinx, Inc.}},
- title = {{ISE WebPACK Design Software}},
- note = {\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}}
-}
-
-@misc{QuartusWeb,
- author = {{Altera, Inc.}},
- title = {{Quartus II Web Edition Software}},
- note = {\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}}
-}
-
-@misc{OR1200,
- title = {{OpenRISC 1200 CPU}},
- note = {\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}}
-}
-
-@misc{openMSP430,
- title = {{openMSP430 CPU}},
- note = {\url{http://opencores.org/project,openmsp430}}
-}
-
-@misc{i2cmaster,
- title = {{OpenCores I$^2$C Core}},
- note = {\url{http://opencores.org/project,i2c}}
-}
-
-@misc{k68,
- title = {{OpenCores k68 Core}},
- note = {\url{http://opencores.org/project,k68}}
-}
-
-@misc{bison,
- title = {{GNU Bison}},
- note = {\url{http://www.gnu.org/software/bison/}}
-}
-
-@misc{flex,
- title = {{Flex}},
- note = {\url{http://flex.sourceforge.net/}}
-}
-
-@misc{C_to_Verilog,
- title = {{C-to-Verilog}},
- note = {\url{http://www.c-to-verilog.com/}}
-}
-
-@misc{LegUp,
- title = {{LegUp}},
- note = {\url{http://legup.eecg.utoronto.ca/}}
-}
-
-@misc{LibertyFormat,
- title = {{The Liberty Library Modeling Standard}},
- note = {\url{http://www.opensourceliberty.org/}}
-}
-
-@misc{ASIC-WORLD,
- title = {{World of ASIC}},
- note = {\url{http://www.asic-world.com/}}
-}
-
-@misc{Formality,
- title = {{Synopsys Formality Equivalence Checking}},
- note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}},
-}
-
-@misc{bigint,
- author = {Matt McCutchen},
- title = {{C++ Big Integer Library}},
- note = {\url{http://mattmccutchen.net/bigint/}}
-}
-
+ +@misc{YosysGit, + author = {Clifford Wolf}, + title = {{Yosys Open SYnthesis Suite (YOSYS)}}, + note = {\url{http://github.com/cliffordwolf/yosys}} +} + +@misc{YosysTestsGit, + author = {Clifford Wolf}, + title = {{Yosys Test Bench}}, + note = {\url{http://github.com/cliffordwolf/yosys-tests}} +} + +@misc{VlogHammer, + author = {Clifford Wolf}, + title = {{VlogHammer Verilog Synthesis Regression Tests}}, + note = {\url{http://github.com/cliffordwolf/VlogHammer}} +} + +@misc{Icarus, + author = {Stephen Williams}, + title = {{Icarus Verilog}}, + note = {Version 0.8.7, \url{http://iverilog.icarus.com/}} +} + +@misc{VTR, + author= {Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson}, + title = {{The Verilog-to-Routing (VTR) Project for FPGAs}}, + note = {Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}} +} + +@misc{HANA, + author = {Parvez Ahmad}, + title = {{HDL Analyzer and Netlist Architect (HANA)}}, + note = {Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}} +} + +@misc{MVSIS, + author = {MVSIS group at Berkeley studies logic synthesis and verification for VLSI design}, + title = {{MVSIS: Logic Synthesis and Verification}}, + note = {Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}} +} + +@misc{VIS, + author = {{The VIS group}}, + title = {{VIS: A system for Verification and Synthesis}}, + note = {Version 2.4, \url{http://vlsi.colorado.edu/~vis/}} +} + +@misc{ABC, + author = {{Berkeley Logic Synthesis and Verification Group}}, + title = {{ABC: A System for Sequential Synthesis and Verification}}, + note = {HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}} +} + +@misc{AIGER, + author = {{Armin Biere, Johannes Kepler University Linz, Austria}}, + title = {{AIGER}}, + note = {\url{http://fmv.jku.at/aiger/}} +} + +@misc{XilinxWebPACK, + author = {{Xilinx, Inc.}}, + title = {{ISE WebPACK Design Software}}, + note = {\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}} +} + +@misc{QuartusWeb, + author = {{Altera, Inc.}}, + title = {{Quartus II Web Edition Software}}, + note = {\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}} +} + +@misc{OR1200, + title = {{OpenRISC 1200 CPU}}, + note = {\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}} +} + +@misc{openMSP430, + title = {{openMSP430 CPU}}, + note = {\url{http://opencores.org/project,openmsp430}} +} + +@misc{i2cmaster, + title = {{OpenCores I$^2$C Core}}, + note = {\url{http://opencores.org/project,i2c}} +} + +@misc{k68, + title = {{OpenCores k68 Core}}, + note = {\url{http://opencores.org/project,k68}} +} + +@misc{bison, + title = {{GNU Bison}}, + note = {\url{http://www.gnu.org/software/bison/}} +} + +@misc{flex, + title = {{Flex}}, + note = {\url{http://flex.sourceforge.net/}} +} + +@misc{C_to_Verilog, + title = {{C-to-Verilog}}, + note = {\url{http://www.c-to-verilog.com/}} +} + +@misc{LegUp, + title = {{LegUp}}, + note = {\url{http://legup.eecg.utoronto.ca/}} +} + +@misc{LibertyFormat, + title = {{The Liberty Library Modeling Standard}}, + note = {\url{http://www.opensourceliberty.org/}} +} + +@misc{ASIC-WORLD, + title = {{World of ASIC}}, + note = {\url{http://www.asic-world.com/}} +} + +@misc{Formality, + title = {{Synopsys Formality Equivalence Checking}}, + note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}}, +} + +@misc{bigint, + author = {Matt McCutchen}, + title = {{C++ Big Integer Library}}, + note = {\url{http://mattmccutchen.net/bigint/}} +} + diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 4acb5aef5..43a43b4fc 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -18,7 +18,7 @@ */ // [[CITE]] Tarjan's strongly connected components algorithm -// Tarjan, R. E. (1972), "Depth-first search and linear graph algorithms", SIAM Journal on Computing 1 (2): 146–160, doi:10.1137/0201010 +// Tarjan, R. E. (1972), "Depth-first search and linear graph algorithms", SIAM Journal on Computing 1 (2): 146-160, doi:10.1137/0201010 // http://en.wikipedia.org/wiki/Tarjan's_strongly_connected_components_algorithm #include "kernel/register.h" diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 1449f2e8a..c19593f05 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -26,7 +26,7 @@ // http://www.ece.cmu.edu/~ee760/760docs/blif.pdf // [[CITE]] Kahn's Topological sorting algorithm -// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025 +// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting #define ABC_COMMAND_LIB "strash; scorr; ifraig; retime {D}; strash; dch -f; map {D}" diff --git a/tests/asicworld/code_hdl_models_arbiter.v b/tests/asicworld/code_hdl_models_arbiter.v index 978e1987b..d3e3a66f1 100644 --- a/tests/asicworld/code_hdl_models_arbiter.v +++ b/tests/asicworld/code_hdl_models_arbiter.v @@ -1,123 +1,123 @@ -//----------------------------------------------------
-// A four level, round-robin arbiter. This was
-// orginally coded by WD Peterson in VHDL.
-//----------------------------------------------------
-module arbiter (
- clk,
- rst,
- req3,
- req2,
- req1,
- req0,
- gnt3,
- gnt2,
- gnt1,
- gnt0
-);
-// --------------Port Declaration-----------------------
-input clk;
-input rst;
-input req3;
-input req2;
-input req1;
-input req0;
-output gnt3;
-output gnt2;
-output gnt1;
-output gnt0;
-
-//--------------Internal Registers----------------------
-wire [1:0] gnt ;
-wire comreq ;
-wire beg ;
-wire [1:0] lgnt ;
-wire lcomreq ;
-reg lgnt0 ;
-reg lgnt1 ;
-reg lgnt2 ;
-reg lgnt3 ;
-reg lasmask ;
-reg lmask0 ;
-reg lmask1 ;
-reg ledge ;
-
-//--------------Code Starts Here-----------------------
-always @ (posedge clk)
-if (rst) begin
- lgnt0 <= 0;
- lgnt1 <= 0;
- lgnt2 <= 0;
- lgnt3 <= 0;
-end else begin
- lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
- | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
- | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
- | (~lcomreq & lmask1 & lmask0 & req0 )
- | ( lcomreq & lgnt0 );
- lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
- | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)
- | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)
- | (~lcomreq & lmask1 & lmask0 & req1 & ~req0)
- | ( lcomreq & lgnt1);
- lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)
- | (~lcomreq & ~lmask1 & lmask0 & req2)
- | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)
- | (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)
- | ( lcomreq & lgnt2);
- lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)
- | (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)
- | (~lcomreq & lmask1 & ~lmask0 & req3)
- | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
- | ( lcomreq & lgnt3);
-end
-
-//----------------------------------------------------
-// lasmask state machine.
-//----------------------------------------------------
-assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
-always @ (posedge clk)
-begin
- lasmask <= (beg & ~ledge & ~lasmask);
- ledge <= (beg & ~ledge & lasmask)
- | (beg & ledge & ~lasmask);
-end
-
-//----------------------------------------------------
-// comreq logic.
-//----------------------------------------------------
-assign lcomreq = ( req3 & lgnt3 )
- | ( req2 & lgnt2 )
- | ( req1 & lgnt1 )
- | ( req0 & lgnt0 );
-
-//----------------------------------------------------
-// Encoder logic.
-//----------------------------------------------------
-assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
-
-//----------------------------------------------------
-// lmask register.
-//----------------------------------------------------
-always @ (posedge clk )
-if( rst ) begin
- lmask1 <= 0;
- lmask0 <= 0;
-end else if(lasmask) begin
- lmask1 <= lgnt[1];
- lmask0 <= lgnt[0];
-end else begin
- lmask1 <= lmask1;
- lmask0 <= lmask0;
-end
-
-assign comreq = lcomreq;
-assign gnt = lgnt;
-//----------------------------------------------------
-// Drive the outputs
-//----------------------------------------------------
-assign gnt3 = lgnt3;
-assign gnt2 = lgnt2;
-assign gnt1 = lgnt1;
-assign gnt0 = lgnt0;
-
-endmodule
+//---------------------------------------------------- +// A four level, round-robin arbiter. This was +// orginally coded by WD Peterson in VHDL. +//---------------------------------------------------- +module arbiter ( + clk, + rst, + req3, + req2, + req1, + req0, + gnt3, + gnt2, + gnt1, + gnt0 +); +// --------------Port Declaration----------------------- +input clk; +input rst; +input req3; +input req2; +input req1; +input req0; +output gnt3; +output gnt2; +output gnt1; +output gnt0; + +//--------------Internal Registers---------------------- +wire [1:0] gnt ; +wire comreq ; +wire beg ; +wire [1:0] lgnt ; +wire lcomreq ; +reg lgnt0 ; +reg lgnt1 ; +reg lgnt2 ; +reg lgnt3 ; +reg lasmask ; +reg lmask0 ; +reg lmask1 ; +reg ledge ; + +//--------------Code Starts Here----------------------- +always @ (posedge clk) +if (rst) begin + lgnt0 <= 0; + lgnt1 <= 0; + lgnt2 <= 0; + lgnt3 <= 0; +end else begin + lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0) + | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0) + | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0) + | (~lcomreq & lmask1 & lmask0 & req0 ) + | ( lcomreq & lgnt0 ); + lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1) + | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0) + | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0) + | (~lcomreq & lmask1 & lmask0 & req1 & ~req0) + | ( lcomreq & lgnt1); + lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1) + | (~lcomreq & ~lmask1 & lmask0 & req2) + | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0) + | (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0) + | ( lcomreq & lgnt2); + lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1) + | (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2) + | (~lcomreq & lmask1 & ~lmask0 & req3) + | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0) + | ( lcomreq & lgnt3); +end + +//---------------------------------------------------- +// lasmask state machine. +//---------------------------------------------------- +assign beg = (req3 | req2 | req1 | req0) & ~lcomreq; +always @ (posedge clk) +begin + lasmask <= (beg & ~ledge & ~lasmask); + ledge <= (beg & ~ledge & lasmask) + | (beg & ledge & ~lasmask); +end + +//---------------------------------------------------- +// comreq logic. +//---------------------------------------------------- +assign lcomreq = ( req3 & lgnt3 ) + | ( req2 & lgnt2 ) + | ( req1 & lgnt1 ) + | ( req0 & lgnt0 ); + +//---------------------------------------------------- +// Encoder logic. +//---------------------------------------------------- +assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)}; + +//---------------------------------------------------- +// lmask register. +//---------------------------------------------------- +always @ (posedge clk ) +if( rst ) begin + lmask1 <= 0; + lmask0 <= 0; +end else if(lasmask) begin + lmask1 <= lgnt[1]; + lmask0 <= lgnt[0]; +end else begin + lmask1 <= lmask1; + lmask0 <= lmask0; +end + +assign comreq = lcomreq; +assign gnt = lgnt; +//---------------------------------------------------- +// Drive the outputs +//---------------------------------------------------- +assign gnt3 = lgnt3; +assign gnt2 = lgnt2; +assign gnt1 = lgnt1; +assign gnt0 = lgnt0; + +endmodule diff --git a/tests/asicworld/code_hdl_models_t_gate_switch.v b/tests/asicworld/code_hdl_models_t_gate_switch.v index 1bff66af8..5a7e0eaff 100644 --- a/tests/asicworld/code_hdl_models_t_gate_switch.v +++ b/tests/asicworld/code_hdl_models_t_gate_switch.v @@ -1,11 +1,11 @@ -module t_gate_switch (L,R,nC,C);
- inout L;
- inout R;
- input nC;
- input C;
-
- //Syntax: keyword unique_name (drain. source, gate);
- pmos p1 (L,R,nC);
- nmos p2 (L,R,C);
-
-endmodule
+module t_gate_switch (L,R,nC,C); + inout L; + inout R; + input nC; + input C; + + //Syntax: keyword unique_name (drain. source, gate); + pmos p1 (L,R,nC); + nmos p2 (L,R,C); + +endmodule diff --git a/tests/asicworld/code_hdl_models_up_counter.v b/tests/asicworld/code_hdl_models_up_counter.v index ffe670994..e05302182 100644 --- a/tests/asicworld/code_hdl_models_up_counter.v +++ b/tests/asicworld/code_hdl_models_up_counter.v @@ -2,7 +2,7 @@ // Design Name : up_counter // File Name : up_counter.v // Function : Up counter -// Coder : Deepak +// Coder : Deepak //----------------------------------------------------- module up_counter ( out , // Output of the counter diff --git a/tests/asicworld/code_verilog_tutorial_counter.v b/tests/asicworld/code_verilog_tutorial_counter.v index 534519745..10ca00df4 100644 --- a/tests/asicworld/code_verilog_tutorial_counter.v +++ b/tests/asicworld/code_verilog_tutorial_counter.v @@ -1,19 +1,19 @@ -//-----------------------------------------------------
-// Design Name : counter
-// File Name : counter.v
-// Function : 4 bit up counter
-// Coder : Deepak
-//-----------------------------------------------------
-module counter (clk, reset, enable, count);
-input clk, reset, enable;
-output [3:0] count;
-reg [3:0] count;
-
-always @ (posedge clk)
-if (reset == 1'b1) begin
- count <= 0;
-end else if ( enable == 1'b1) begin
- count <= count + 1;
-end
-
-endmodule
+//----------------------------------------------------- +// Design Name : counter +// File Name : counter.v +// Function : 4 bit up counter +// Coder : Deepak +//----------------------------------------------------- +module counter (clk, reset, enable, count); +input clk, reset, enable; +output [3:0] count; +reg [3:0] count; + +always @ (posedge clk) +if (reset == 1'b1) begin + count <= 0; +end else if ( enable == 1'b1) begin + count <= count + 1; +end + +endmodule diff --git a/tests/asicworld/code_verilog_tutorial_counter_tb.v b/tests/asicworld/code_verilog_tutorial_counter_tb.v index 104779381..504814543 100644 --- a/tests/asicworld/code_verilog_tutorial_counter_tb.v +++ b/tests/asicworld/code_verilog_tutorial_counter_tb.v @@ -1,113 +1,113 @@ -///////////////////////////////////////////////////////////////////////////
-// MODULE : counter_tb //
-// TOP MODULE : -- //
-// //
-// PURPOSE : 4-bit up counter test bench //
-// //
-// DESIGNER : Deepak Kumar Tala //
-// //
-// Revision History //
-// //
-// DEVELOPMENT HISTORY : //
-// Rev0.0 : Jan 03, 2003 //
-// Initial Revision //
-// //
-///////////////////////////////////////////////////////////////////////////
-module testbench;
-
-reg clk, reset, enable;
-wire [3:0] count;
-reg dut_error;
-
-counter U0 (
-.clk (clk),
-.reset (reset),
-.enable (enable),
-.count (count)
-);
-
-event reset_enable;
-event terminate_sim;
-
-initial
-begin
- $display ("###################################################");
- clk = 0;
- reset = 0;
- enable = 0;
- dut_error = 0;
-end
-
-always
- #5 clk = !clk;
-
-initial
-begin
- $dumpfile ("counter.vcd");
- $dumpvars;
-end
-
-
-initial
-@ (terminate_sim) begin
- $display ("Terminating simulation");
- if (dut_error == 0) begin
- $display ("Simulation Result : PASSED");
- end
- else begin
- $display ("Simulation Result : FAILED");
- end
- $display ("###################################################");
- #1 $finish;
-end
-
-
-
-event reset_done;
-
-initial
-forever begin
- @ (reset_enable);
- @ (negedge clk)
- $display ("Applying reset");
- reset = 1;
- @ (negedge clk)
- reset = 0;
- $display ("Came out of Reset");
- -> reset_done;
-end
-
-initial begin
- #10 -> reset_enable;
- @ (reset_done);
- @ (negedge clk);
- enable = 1;
- repeat (5)
- begin
- @ (negedge clk);
- end
- enable = 0;
- #5 -> terminate_sim;
-end
-
-
-reg [3:0] count_compare;
-
-always @ (posedge clk)
-if (reset == 1'b1)
- count_compare <= 0;
-else if ( enable == 1'b1)
- count_compare <= count_compare + 1;
-
-
-
-always @ (negedge clk)
-if (count_compare != count) begin
- $display ("DUT ERROR AT TIME%d",$time);
- $display ("Expected value %d, Got Value %d", count_compare, count);
- dut_error = 1;
- #5 -> terminate_sim;
-end
-
-endmodule
-
+/////////////////////////////////////////////////////////////////////////// +// MODULE : counter_tb // +// TOP MODULE : -- // +// // +// PURPOSE : 4-bit up counter test bench // +// // +// DESIGNER : Deepak Kumar Tala // +// // +// Revision History // +// // +// DEVELOPMENT HISTORY : // +// Rev0.0 : Jan 03, 2003 // +// Initial Revision // +// // +/////////////////////////////////////////////////////////////////////////// +module testbench; + +reg clk, reset, enable; +wire [3:0] count; +reg dut_error; + +counter U0 ( +.clk (clk), +.reset (reset), +.enable (enable), +.count (count) +); + +event reset_enable; +event terminate_sim; + +initial +begin + $display ("###################################################"); + clk = 0; + reset = 0; + enable = 0; + dut_error = 0; +end + +always + #5 clk = !clk; + +initial +begin + $dumpfile ("counter.vcd"); + $dumpvars; +end + + +initial +@ (terminate_sim) begin + $display ("Terminating simulation"); + if (dut_error == 0) begin + $display ("Simulation Result : PASSED"); + end + else begin + $display ("Simulation Result : FAILED"); + end + $display ("###################################################"); + #1 $finish; +end + + + +event reset_done; + +initial +forever begin + @ (reset_enable); + @ (negedge clk) + $display ("Applying reset"); + reset = 1; + @ (negedge clk) + reset = 0; + $display ("Came out of Reset"); + -> reset_done; +end + +initial begin + #10 -> reset_enable; + @ (reset_done); + @ (negedge clk); + enable = 1; + repeat (5) + begin + @ (negedge clk); + end + enable = 0; + #5 -> terminate_sim; +end + + +reg [3:0] count_compare; + +always @ (posedge clk) +if (reset == 1'b1) + count_compare <= 0; +else if ( enable == 1'b1) + count_compare <= count_compare + 1; + + + +always @ (negedge clk) +if (count_compare != count) begin + $display ("DUT ERROR AT TIME%d",$time); + $display ("Expected value %d, Got Value %d", count_compare, count); + dut_error = 1; + #5 -> terminate_sim; +end + +endmodule + |