diff options
| -rw-r--r-- | frontends/ast/simplify.cc | 17 | ||||
| -rw-r--r-- | tests/simple/rotate.v | 48 |
2 files changed, 61 insertions, 4 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 6d662c8f7..636dde48e 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -383,7 +383,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } assert(children[1]->type == AST_IDENTIFIER); newNode = children[1]->clone(); - newNode->str = stringf("%s[%d].%s", str.c_str(), children[0]->integer, children[1]->str.c_str()); + const char *second_part = children[1]->str.c_str(); + if (second_part[0] == '\\') + second_part++; + newNode->str = stringf("%s[%d].%s", str.c_str(), children[0]->integer, second_part); goto apply_newNode; } @@ -599,8 +602,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, buf->expand_genblock(varbuf->str, sstr.str(), name_map); if (type == AST_GENFOR) { - for (size_t i = 0; i < buf->children.size(); i++) + for (size_t i = 0; i < buf->children.size(); i++) { + buf->children[i]->simplify(false, false, false, stage, -1, false); current_ast_mod->children.push_back(buf->children[i]); + } } else { for (size_t i = 0; i < buf->children.size(); i++) current_block->children.insert(current_block->children.begin() + current_block_idx++, buf->children[i]); @@ -633,8 +638,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, expand_genblock(std::string(), str + ".", name_map); } - for (size_t i = 0; i < children.size(); i++) + for (size_t i = 0; i < children.size(); i++) { + children[i]->simplify(false, false, false, stage, -1, false); current_ast_mod->children.push_back(children[i]); + } children.clear(); did_something = true; @@ -668,8 +675,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, buf->expand_genblock(std::string(), buf->str + ".", name_map); } - for (size_t i = 0; i < buf->children.size(); i++) + for (size_t i = 0; i < buf->children.size(); i++) { + buf->children[i]->simplify(false, false, false, stage, -1, false); current_ast_mod->children.push_back(buf->children[i]); + } buf->children.clear(); delete buf; diff --git a/tests/simple/rotate.v b/tests/simple/rotate.v new file mode 100644 index 000000000..eb832e6f5 --- /dev/null +++ b/tests/simple/rotate.v @@ -0,0 +1,48 @@ + +// test case taken from amber23 verilog code +module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod); + +input [31:0] i_in; +input direction; +input [4:0] shift_amount; +output [31:0] rot_prod; + +// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs. +// Practically a bit higher due to high fanout of "direction". +generate +genvar i, j; + for (i = 0; i < 5; i = i + 1) + begin : netgen + wire [31:0] in; + reg [31:0] out; + for (j = 0; j < 32; j = j + 1) + begin : net + always @* + out[j] = in[j] & (~shift_amount[i] ^ direction) | + in[wrap(j, i)] & (shift_amount[i] ^ direction); + end + end + + // Order is reverted with respect to volatile shift_amount[0] + assign netgen[4].in = i_in; + for (i = 1; i < 5; i = i + 1) + begin : router + assign netgen[i-1].in = netgen[i].out; + end +endgenerate + +// Aliasing +assign rot_prod = netgen[0].out; + +function [4:0] wrap; +input integer pos; +input integer level; +integer out; +begin + out = pos - (1 << level); + wrap = out[4:0]; +end +endfunction + +endmodule + |