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-rw-r--r--.github/workflows/codeql.yml2
-rw-r--r--.github/workflows/emcc.yml6
-rw-r--r--.github/workflows/test-linux.yml4
-rw-r--r--.github/workflows/test-macos.yml4
-rw-r--r--.github/workflows/version.yml6
-rw-r--r--.github/workflows/vs.yml8
-rw-r--r--Makefile2
-rw-r--r--backends/smt2/smtbmc.py3
-rw-r--r--libs/fst/fstapi.cc2
-rw-r--r--techlibs/common/Makefile.inc1
-rw-r--r--techlibs/common/smtmap.v28
-rwxr-xr-xtests/sim/run-test.sh2
12 files changed, 48 insertions, 20 deletions
diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml
index 57cbe5010..2a046703b 100644
--- a/.github/workflows/codeql.yml
+++ b/.github/workflows/codeql.yml
@@ -14,7 +14,7 @@ jobs:
run: sudo apt-get install bison flex libreadline-dev tcl-dev libffi-dev
- name: Checkout repository
- uses: actions/checkout@v3.0.0
+ uses: actions/checkout@v3
- name: Initialize CodeQL
uses: github/codeql-action/init@v2
diff --git a/.github/workflows/emcc.yml b/.github/workflows/emcc.yml
index f1cc4b3e7..7a9a6064f 100644
--- a/.github/workflows/emcc.yml
+++ b/.github/workflows/emcc.yml
@@ -7,10 +7,10 @@ jobs:
runs-on: ubuntu-latest
steps:
- uses: mymindstorm/setup-emsdk@v11
- - uses: actions/checkout@v2
+ - uses: actions/checkout@v3
- name: Cache sources
id: cache-sources
- uses: actions/cache@v2
+ uses: actions/cache@v3
with:
path: .
key: cache-yosys
@@ -18,7 +18,7 @@ jobs:
run: |
make config-emcc
make YOSYS_VER=latest
- - uses: actions/upload-artifact@v2
+ - uses: actions/upload-artifact@v3
with:
name: yosysjs
path: yosysjs-latest.zip
diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index e27ea37d2..b974757c4 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -84,7 +84,7 @@ jobs:
$CXX --version
- name: Checkout Yosys
- uses: actions/checkout@v2
+ uses: actions/checkout@v3
- name: Get iverilog
shell: bash
@@ -93,7 +93,7 @@ jobs:
- name: Cache iverilog
id: cache-iverilog
- uses: actions/cache@v2
+ uses: actions/cache@v3
with:
path: .local/
key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
diff --git a/.github/workflows/test-macos.yml b/.github/workflows/test-macos.yml
index 22cf5e658..048457234 100644
--- a/.github/workflows/test-macos.yml
+++ b/.github/workflows/test-macos.yml
@@ -35,7 +35,7 @@ jobs:
cc --version
- name: Checkout Yosys
- uses: actions/checkout@v2
+ uses: actions/checkout@v3
- name: Get iverilog
shell: bash
@@ -44,7 +44,7 @@ jobs:
- name: Cache iverilog
id: cache-iverilog
- uses: actions/cache@v2
+ uses: actions/cache@v3
with:
path: .local/
key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
diff --git a/.github/workflows/version.yml b/.github/workflows/version.yml
index c6f4da30d..c2a1756e9 100644
--- a/.github/workflows/version.yml
+++ b/.github/workflows/version.yml
@@ -10,15 +10,15 @@ jobs:
runs-on: ubuntu-latest
steps:
- name: Checkout
- uses: actions/checkout@v2
+ uses: actions/checkout@v3
with:
fetch-depth: 0
- name: Take last commit
id: log
- run: echo "::set-output name=message::$(git log --no-merges -1 --oneline)"
+ run: echo "message=$(git log --no-merges -1 --oneline)" >> $GITHUB_OUTPUT
- name: Take repository
id: repo
- run: echo "::set-output name=message::$GITHUB_REPOSITORY"
+ run: echo "message=$GITHUB_REPOSITORY" >> $GITHUB_OUTPUT
- name: Bump version
if: "!contains(steps.log.outputs.message, 'Bump version') && contains(steps.repo.outputs.message, 'YosysHQ/yosys')"
run: |
diff --git a/.github/workflows/vs.yml b/.github/workflows/vs.yml
index 79a8401d6..744ad5677 100644
--- a/.github/workflows/vs.yml
+++ b/.github/workflows/vs.yml
@@ -6,16 +6,16 @@ jobs:
yosys-vcxsrc:
runs-on: ubuntu-latest
steps:
- - uses: actions/checkout@v2
+ - uses: actions/checkout@v3
- name: Cache sources
id: cache-sources
- uses: actions/cache@v2
+ uses: actions/cache@v3
with:
path: .
key: cache-yosys
- name: Build
run: make vcxsrc YOSYS_VER=latest
- - uses: actions/upload-artifact@v2
+ - uses: actions/upload-artifact@v3
with:
name: vcxsrc
path: yosys-win32-vcxsrc-latest.zip
@@ -24,7 +24,7 @@ jobs:
runs-on: windows-2019
needs: yosys-vcxsrc
steps:
- - uses: actions/download-artifact@v2
+ - uses: actions/download-artifact@v3
with:
name: vcxsrc
path: .
diff --git a/Makefile b/Makefile
index 52338120e..7802a3cc3 100644
--- a/Makefile
+++ b/Makefile
@@ -131,7 +131,7 @@ LDLIBS += -lrt
endif
endif
-YOSYS_VER := 0.22+39
+YOSYS_VER := 0.22+42
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo
diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index 4c1f07229..cb21eb3aa 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -453,7 +453,6 @@ assert topmod in smt.modinfo
if cexfile is not None:
if not got_topt:
- assume_skipped = 0
skip_steps = 0
num_steps = 0
@@ -499,7 +498,6 @@ if aimfile is not None:
latch_map = dict()
if not got_topt:
- assume_skipped = 0
skip_steps = 0
num_steps = 0
@@ -633,7 +631,6 @@ if aimfile is not None:
if inywfile is not None:
if not got_topt:
- assume_skipped = 0
skip_steps = 0
num_steps = 0
diff --git a/libs/fst/fstapi.cc b/libs/fst/fstapi.cc
index b79470db3..da0d959a0 100644
--- a/libs/fst/fstapi.cc
+++ b/libs/fst/fstapi.cc
@@ -3607,6 +3607,7 @@ static int fstReaderRecreateHierFile(struct fstReaderContext *xc)
fflush(xc->f);
#endif
zfd = dup(fileno(xc->f));
+ lseek(zfd, ftell(xc->f), SEEK_SET);
zhandle = gzdopen(zfd, "rb");
if (!zhandle) {
close(zfd);
@@ -4272,6 +4273,7 @@ int fstReaderInit(struct fstReaderContext *xc)
#endif
zfd = dup(fileno(xc->f));
+ lseek(zfd, ftell(xc->f), SEEK_SET);
zhandle = gzdopen(zfd, "rb");
if (zhandle) {
for (offpnt = 0; offpnt < uclen; offpnt += FST_GZIO_LEN) {
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 607e772a2..47f1ed604 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -22,6 +22,7 @@ kernel/register.o: techlibs/common/simlib_help.inc techlibs/common/simcells_help
$(eval $(call add_share_file,share,techlibs/common/simlib.v))
$(eval $(call add_share_file,share,techlibs/common/simcells.v))
$(eval $(call add_share_file,share,techlibs/common/techmap.v))
+$(eval $(call add_share_file,share,techlibs/common/smtmap.v))
$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
$(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
diff --git a/techlibs/common/smtmap.v b/techlibs/common/smtmap.v
new file mode 100644
index 000000000..8c7503dc8
--- /dev/null
+++ b/techlibs/common/smtmap.v
@@ -0,0 +1,28 @@
+(* techmap_celltype = "$pmux" *)
+module smt_pmux (A, B, S, Y);
+ parameter WIDTH = 1;
+ parameter S_WIDTH = 1;
+
+ (* force_downto *)
+ input [WIDTH-1:0] A;
+ (* force_downto *)
+ input [WIDTH*S_WIDTH-1:0] B;
+ (* force_downto *)
+ input [S_WIDTH-1:0] S;
+ (* force_downto *)
+ output [WIDTH-1:0] Y;
+
+ (* force_downto *)
+ wire [WIDTH-1:0] Y_B;
+
+ genvar i, j;
+ generate
+ (* force_downto *)
+ wire [WIDTH*(S_WIDTH+1)-1:0] C;
+
+ assign C[WIDTH-1:0] = A;
+ for (i = 0; i < S_WIDTH; i = i + 1)
+ assign C[WIDTH*(i+2)-1:WIDTH*(i+1)] = S[i] ? B[WIDTH*(i+1)-1:WIDTH*i] : C[WIDTH*(i+1)-1:WIDTH*i];
+ assign Y = C[WIDTH*(S_WIDTH+1)-1:WIDTH*S_WIDTH];
+ endgenerate
+endmodule
diff --git a/tests/sim/run-test.sh b/tests/sim/run-test.sh
index d34d1f3c9..a5120e77e 100755
--- a/tests/sim/run-test.sh
+++ b/tests/sim/run-test.sh
@@ -3,7 +3,7 @@ set -eu
source ../gen-tests-makefile.sh
echo "Generate FST for sim models"
find tb/* -name tb*.v | while read name; do
- test_name=$(basename -s .v $name)
+ test_name=$(basename $name .v)
echo "Test $test_name"
verilog_name=${test_name:3}.v
iverilog -o tb/$test_name.out $name $verilog_name
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-26 22:23:51 +0000