diff options
| -rw-r--r-- | frontends/verilog/lexer.l | 11 | ||||
| -rw-r--r-- | passes/abc/blifparse.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/Makefile.inc | 9 | ||||
| -rw-r--r-- | tests/techmap/mem_simple_4x1_runtest.sh | 2 |
4 files changed, 17 insertions, 7 deletions
diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l index 79f44b4a6..e3e5e4ab2 100644 --- a/frontends/verilog/lexer.l +++ b/frontends/verilog/lexer.l @@ -75,6 +75,17 @@ namespace VERILOG_FRONTEND { ln_stack.pop_back(); } +"`line"[ \t]+[^ \t\r\n]+[ \t]+\"[^ \r\n]+\"[^\r\n]*\n { + char *p = yytext + 5; + while (*p == ' ' || *p == '\t') p++; + frontend_verilog_yyset_lineno(atoi(p)); + while (*p && *p != ' ' && *p != '\t') p++; + while (*p == ' ' || *p == '\t') p++; + char *q = *p ? p + 1 : p; + while (*q && *q != '"') q++; + current_filename = std::string(p).substr(1, q-p-1); +} + "`file_notfound "[^\n]* { log_error("Can't open include file `%s'!\n", yytext + 15); } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 2d46d1a8e..1d4da19ad 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -40,7 +40,7 @@ static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, } if (buffer_len == 0 || buffer[buffer_len-1] == '\\') { - if (buffer[buffer_len-1] == '\\') + if (buffer_len > 0 && buffer[buffer_len-1] == '\\') buffer[--buffer_len] = 0; line_count++; if (fgets(buffer+buffer_len, buffer_size-buffer_len, f) == NULL) diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index b83ab8495..85d580ce8 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -10,12 +10,11 @@ OBJS += passes/techmap/extract.o GENFILES += passes/techmap/stdcells.inc passes/techmap/stdcells.inc: techlibs/common/stdcells.v - echo "// autogenerated from $<\n" > $@.new + echo "// autogenerated from $<" > $@.new echo "static char stdcells_code[] = {" >> $@.new - for c in `od -v -td1 -An $<` ; do echo " $$c," >> $@.new ; done - echo " 0 };" >> $@.new - fmt $@.new > $@ - rm -f $@.new + od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new + echo "0};" >> $@.new + mv $@.new $@ passes/techmap/techmap.o: passes/techmap/stdcells.inc diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index 8285875b8..e2c6303da 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -2,7 +2,7 @@ set -ev -yosys -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v +../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v |