diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 | ||||
| -rw-r--r-- | frontends/verific/verific.cc | 1 | ||||
| -rw-r--r-- | kernel/ffmerge.cc | 2 | ||||
| -rw-r--r-- | tests/memories/trans_addr_enable.v | 21 |
5 files changed, 26 insertions, 2 deletions
@@ -127,7 +127,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.10+14 +YOSYS_VER := 0.10+16 GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6fb14d7fc..dc5c188c0 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2062,6 +2062,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); bool keep_running = true; + int cnt = 0; for (int port_id = 1; keep_running; port_id++) { keep_running = false; for (auto wire : module->wires()) { @@ -2070,6 +2071,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) f << stringf(", "); f << stringf("%s", id(wire->name).c_str()); keep_running = true; + if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++; continue; } } diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b8742e61d..74638dc8d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -992,6 +992,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se } else { log("Importing module %s.\n", RTLIL::id2cstr(module->name)); } + import_attributes(module->attributes, nl, nl); SetIter si; MapIter mi, mi2; diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc index 4ca5bcbb4..c65108413 100644 --- a/kernel/ffmerge.cc +++ b/kernel/ffmerge.cc @@ -157,7 +157,7 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pai } bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits) { - ff = FfData(); + ff = FfData(module, initvals, NEW_ID); sigmap->apply(sig); bool found = false; diff --git a/tests/memories/trans_addr_enable.v b/tests/memories/trans_addr_enable.v new file mode 100644 index 000000000..f366f41ad --- /dev/null +++ b/tests/memories/trans_addr_enable.v @@ -0,0 +1,21 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-rd-clk \clk + +module top(input clk, we, rae, input [7:0] addr, wd, output [7:0] rd); + +reg [7:0] mem[0:255]; + +reg [7:0] rra; + +always @(posedge clk) begin + if (we) + mem[addr] <= wd; + + if (rae) + rra <= addr; +end + +assign rd = mem[rra]; + +endmodule |