diff options
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 37 | ||||
| -rw-r--r-- | techlibs/ecp5/dram.txt | 12 | ||||
| -rw-r--r-- | techlibs/ecp5/drams_map.v | 28 |
3 files changed, 76 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 54006218f..06e6133a7 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -52,7 +52,7 @@ module TRELLIS_RAM16X2 ( input RAD0, RAD1, RAD2, RAD3, output DO0, DO1 ); - parameter WCKMUX = "WCK"; + parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; parameter INITVAL_0 = 16'h0000; parameter INITVAL_1 = 16'h0000; @@ -87,6 +87,41 @@ endmodule // --------------------------------------- +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + + reg [3:0] mem[15:0]; + + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= INITVAL[4*i :+ 4]; + end + + wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; + + wire muxwre = (WREMUX == "1") ? 1'b1 : + (WREMUX == "0") ? 1'b0 : + (WREMUX == "INV") ? ~WRE : + WRE; + + always @(posedge muxwck) + if (muxwre) + mem[WAD] <= DI; + + assign DO = mem[RAD]; +endmodule + +// --------------------------------------- + module DPR16X4C ( input [3:0] DI, input WCK, WRE, diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt new file mode 100644 index 000000000..a13111f0c --- /dev/null +++ b/techlibs/ecp5/dram.txt @@ -0,0 +1,12 @@ +bram $__TRELLIS_DPR16X4 + init 1 + abits 4 + dbits 4 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram diff --git a/techlibs/ecp5/drams_map.v b/techlibs/ecp5/drams_map.v new file mode 100644 index 000000000..3b3de831f --- /dev/null +++ b/techlibs/ecp5/drams_map.v @@ -0,0 +1,28 @@ +module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0] INIT = 64'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + localparam WCKMUX = CLKPOL2 ? "WCK" : "INV"; + + TRELLIS_DPR16X4 #( + .INITVAL(INIT), + .WCKMUX(WCKMUX), + .WREMUX("WRE") + ) _TECHMAP_REPLACE_ ( + .RAD(A1ADDR), + .DO(A1DATA), + + .WAD(B1ADDR), + .DI(B1DATA), + .WCK(CLK1), + .WRE(B1EN) + ); +endmodule |