Fixed CRLF line endings

1 files changed, 19 insertions, 19 deletions

diff --git a/tests/asicworld/code_verilog_tutorial_counter.v b/tests/asicworld/code_verilog_tutorial_counter.v
index 534519745..10ca00df4 100644
--- a/tests/asicworld/code_verilog_tutorial_counter.v
+++ b/tests/asicworld/code_verilog_tutorial_counter.v
@@ -1,19 +1,19 @@
-//-----------------------------------------------------

-// Design Name : counter

-// File Name   : counter.v

-// Function    : 4 bit up counter

-// Coder       : Deepak

-//-----------------------------------------------------

-module counter (clk, reset, enable, count);

-input clk, reset, enable;

-output [3:0] count;

-reg [3:0] count;                                   

-

-always @ (posedge clk)

-if (reset == 1'b1) begin

-  count <= 0;

-end else if ( enable == 1'b1) begin

-  count <= count + 1;

-end

-

-endmodule  

+//-----------------------------------------------------
+// Design Name : counter
+// File Name   : counter.v
+// Function    : 4 bit up counter
+// Coder       : Deepak
+//-----------------------------------------------------
+module counter (clk, reset, enable, count);
+input clk, reset, enable;
+output [3:0] count;
+reg [3:0] count;                                   
+
+always @ (posedge clk)
+if (reset == 1'b1) begin
+  count <= 0;
+end else if ( enable == 1'b1) begin
+  count <= count + 1;
+end
+
+endmodule