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author | Clifford Wolf <clifford@clifford.at> | 2017-10-20 13:16:24 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-10-20 13:16:24 +0200 |
commit | baddb017fe5eb72fbb65d6f89553dc2341663613 (patch) | |
tree | 4bc6c54afcebbf7220f892e06f17bc4ba79951d6 /tests/asicworld/code_verilog_tutorial_comment.v | |
parent | 0a31a0b3ae570007196c4b4dd6c16ba7de7f3ba9 (diff) | |
download | yosys-baddb017fe5eb72fbb65d6f89553dc2341663613.tar.gz yosys-baddb017fe5eb72fbb65d6f89553dc2341663613.tar.bz2 yosys-baddb017fe5eb72fbb65d6f89553dc2341663613.zip |
Remove PSL example from tests/sva/
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_comment.v')
0 files changed, 0 insertions, 0 deletions