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| author | Rupert Swarbrick <rswarbrick@gmail.com> | 2020-04-20 14:41:55 +0100 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-05-13 23:44:48 -0400 |
| commit | 3421979f00664443c77b0899d34438f979b4c51c (patch) | |
| tree | a686e411f785d4df1eb994b1b04bd945f2c7d246 /tests/arch/intel_alm/blockram.ys | |
| parent | 51ed4a7149f64729edeb5ee8419f3303636180e7 (diff) | |
| download | yosys-3421979f00664443c77b0899d34438f979b4c51c.tar.gz yosys-3421979f00664443c77b0899d34438f979b4c51c.tar.bz2 yosys-3421979f00664443c77b0899d34438f979b4c51c.zip | |
Change the type of current_module to Module
The current_module global is needed so that genRTLIL has somewhere to
put cells and wires that it generates as it makes sense of expressions
that it sees. However, that doesn't actually need to be an AstModule:
the Module base class is enough.
This patch should cause no functional change, but the point is that
it's now possible to call genRTLIL with a module that isn't an
AstModule as "current_module". This will be needed for 'bind' support.
Diffstat (limited to 'tests/arch/intel_alm/blockram.ys')
0 files changed, 0 insertions, 0 deletions