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authorAman Goel <amangoel@umich.edu>2019-09-27 12:30:27 -0400
committerGitHub <noreply@github.com>2019-09-27 12:30:27 -0400
commitcb0dc6e68b9432edc9c30c153954be53c8576911 (patch)
treec137f970f949117d04632158d73bfe1f9c146e6f /techlibs/ice40/arith_map.v
parent4d343fc1cdafe469484846051680ca0b1f948549 (diff)
parent4b15cf5f76e2226bbce1a73d1e0ff54fbf093fe8 (diff)
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Merge pull request #7 from YosysHQ/master
Syncing with official repo
Diffstat (limited to 'techlibs/ice40/arith_map.v')
-rw-r--r--techlibs/ice40/arith_map.v24
1 files changed, 10 insertions, 14 deletions
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 4449fdc1b..26b24db9e 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,23 +44,19 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
- SB_CARRY carry (
- .I0(AA[i]),
- .I1(BB[i]),
+ \$__ICE40_CARRY_WRAPPER #(
+ // A[0]: 1010 1010 1010 1010
+ // A[1]: 1100 1100 1100 1100
+ // A[2]: 1111 0000 1111 0000
+ // A[3]: 1111 1111 0000 0000
+ .LUT(16'b 0110_1001_1001_0110)
+ ) fadd (
+ .A(AA[i]),
+ .B(BB[i]),
.CI(C[i]),
- .CO(CO[i])
- );
- SB_LUT4 #(
- // I0: 1010 1010 1010 1010
- // I1: 1100 1100 1100 1100
- // I2: 1111 0000 1111 0000
- // I3: 1111 1111 0000 0000
- .LUT_INIT(16'b 0110_1001_1001_0110)
- ) adder (
.I0(1'b0),
- .I1(AA[i]),
- .I2(BB[i]),
.I3(C[i]),
+ .CO(CO[i]),
.O(Y[i])
);
end endgenerate