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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 12:14:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 12:14:23 -0700 |
| commit | 7b3a4a1fff297481a463f27da250af8436041753 (patch) | |
| tree | 28b3946564836b2050896db7d9b8886b12a6f9d3 /passes | |
| parent | 73b7ea713ce5d796985678b2732b3a5259d43639 (diff) | |
| download | yosys-7b3a4a1fff297481a463f27da250af8436041753.tar.gz yosys-7b3a4a1fff297481a463f27da250af8436041753.tar.bz2 yosys-7b3a4a1fff297481a463f27da250af8436041753.zip | |
opt_expr: Sx to Sz; spotted by @Xiretza
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 63811c1a1..777a24777 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -175,7 +175,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ } } - bool def = (bit_a != State::Sx && bit_a != State::Sz && bit_b != State::Sx && bit_b != State::Sx); + bool def = (bit_a != State::Sx && bit_a != State::Sz && bit_b != State::Sx && bit_b != State::Sz); if (def || !keepdc) { if (bit_a.wire == NULL && bit_b.wire == NULL) group_idx = GRP_CONST_AB; |