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| author | Aman Goel <amangoel@umich.edu> | 2018-08-18 08:18:40 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-18 08:18:40 +0530 |
| commit | 61f002c908830d59e883d25668b731e7d12470d0 (patch) | |
| tree | 25174f7321f60e14ca6c144544f29971c40abe9b /passes/tests | |
| parent | 5dcb899e76a82c8aa84552a59f4a9f64394e7785 (diff) | |
| parent | e343f3e6d475984c21611474bffe7dcd8f599497 (diff) | |
| download | yosys-61f002c908830d59e883d25668b731e7d12470d0.tar.gz yosys-61f002c908830d59e883d25668b731e7d12470d0.tar.bz2 yosys-61f002c908830d59e883d25668b731e7d12470d0.zip | |
Merge pull request #3 from YosysHQ/master
Updates from official repo
Diffstat (limited to 'passes/tests')
| -rw-r--r-- | passes/tests/test_abcloop.cc | 4 | ||||
| -rw-r--r-- | passes/tests/test_autotb.cc | 4 | ||||
| -rw-r--r-- | passes/tests/test_cell.cc | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index 09cb41954..5d5466afe 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -244,7 +244,7 @@ static void test_abcloop() struct TestAbcloopPass : public Pass { TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -259,7 +259,7 @@ struct TestAbcloopPass : public Pass { log(" use this value as rng seed value (default = unix time).\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design*) + void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE { int num_iter = 100; xorshift32_state = 0; diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index cb31056f4..bfb1d6642 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -324,7 +324,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s struct TestAutotbBackend : public Backend { TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -349,7 +349,7 @@ struct TestAutotbBackend : public Backend { log(" number of iterations the test bench should run (default = 1000)\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { int num_iter = 1000; int seed = 0; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 47b6bdf23..e360b5edb 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -652,7 +652,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: struct TestCellPass : public Pass { TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -712,7 +712,7 @@ struct TestCellPass : public Pass { log(" create a Verilog test bench to test simlib and write_verilog\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design*) + void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE { int num_iter = 100; std::string techmap_cmd = "techmap -assert"; |