diff options
| author | whitequark <whitequark@whitequark.org> | 2020-06-26 07:30:27 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-26 07:30:27 +0000 |
| commit | 12c016ebdc61d3eba681579e7b0b4d81672e498f (patch) | |
| tree | a4b2953cb6ea25865915721b71d2f22a1e06f725 /frontends/verific/example.sv | |
| parent | d6bdc09422e89c30207810cf00021b9ea37991e7 (diff) | |
| parent | 39c39848a21dc4f4a2c3b17842d854047ba6c16f (diff) | |
| download | yosys-12c016ebdc61d3eba681579e7b0b4d81672e498f.tar.gz yosys-12c016ebdc61d3eba681579e7b0b4d81672e498f.tar.bz2 yosys-12c016ebdc61d3eba681579e7b0b4d81672e498f.zip | |
Merge pull request #2188 from antmicro/missing-operators
Add logic-assignments operators
Diffstat (limited to 'frontends/verific/example.sv')
0 files changed, 0 insertions, 0 deletions