From f7354d092ddcb6020f1fc0a23267920884cf8641 Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 10 Aug 2022 15:47:22 +0100 Subject: nexus: Add timing data for LRAM Signed-off-by: gatecat --- nexus/pack.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'nexus/pack.cc') diff --git a/nexus/pack.cc b/nexus/pack.cc index 0aa61144..e727364d 100644 --- a/nexus/pack.cc +++ b/nexus/pack.cc @@ -2614,6 +2614,19 @@ void Arch::assignCellInfo(CellInfo *cell) cell->tmg_index = get_cell_timing_idx(id(str_or_default(cell->params, id_MODE, "DP16K") + "_MODE")); NPNR_ASSERT(cell->tmg_index != -1); + } else if (cell->type == id_LRAM_CORE) { + // Strip off bus indices to get the timing ports + // as timing is generally word-wide + for (const auto &port : cell->ports) { + const std::string &name = port.first.str(this); + size_t idx_end = name.find_last_not_of("0123456789"); + std::string base = name.substr(0, idx_end + 1); + // Strip off bus index + cell->tmg_portmap[port.first] = id(base); + } + + cell->tmg_index = get_cell_timing_idx(id_LRAM_CORE); + NPNR_ASSERT(cell->tmg_index != -1); } else if (is_dsp_cell(cell)) { // Strip off bus indices to get the timing ports // as timing is generally word-wide -- cgit v1.2.3