From 9221acc9e211766d79d7c7dde5d5fc8bb053354d Mon Sep 17 00:00:00 2001 From: gatecat Date: Sat, 15 May 2021 10:26:27 +0100 Subject: mistral: Fix ENA and ACLR bitstream generation Signed-off-by: gatecat --- mistral/globals.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'mistral/globals.cc') diff --git a/mistral/globals.cc b/mistral/globals.cc index 97e35518..9cbabbca 100644 --- a/mistral/globals.cc +++ b/mistral/globals.cc @@ -26,8 +26,8 @@ NEXTPNR_NAMESPACE_BEGIN void Arch::create_clkbuf(int x, int y) { for (int z = 0; z < 4; z++) { - if (z != 2) - continue; // TODO: why do other Zs not work? + if (z != 2) + continue; // TODO: why do other Zs not work? // For now we only consider the input path from general routing, other inputs like dedicated clock pins are // still a TODO BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA); -- cgit v1.2.3