From 386b5b901c9e62d527e84bbd0833f5908f778413 Mon Sep 17 00:00:00 2001 From: gatecat Date: Sun, 9 May 2021 16:51:28 +0100 Subject: mistral: Implement some misc. things Signed-off-by: gatecat --- mistral/globals.cc | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 mistral/globals.cc (limited to 'mistral/globals.cc') diff --git a/mistral/globals.cc b/mistral/globals.cc new file mode 100644 index 00000000..34e569d3 --- /dev/null +++ b/mistral/globals.cc @@ -0,0 +1,37 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2021 gatecat + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "log.h" +#include "nextpnr.h" +#include "util.h" + +NEXTPNR_NAMESPACE_BEGIN + +void Arch::create_clkbuf(int x, int y) +{ + for (int z = 0; z < 4; z++) { + // For now we only consider the input path from general routing, other inputs like dedicated clock pins are + // still a TODO + BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKBUF); + add_bel_pin(bel, id_A, PORT_IN, get_port(CycloneV::CMUXHG, x, y, -1, CycloneV::CLKIN, z)); + add_bel_pin(bel, id_Q, PORT_OUT, get_port(CycloneV::CMUXHG, x, y, z, CycloneV::CLKOUT)); + } +} + +NEXTPNR_NAMESPACE_END -- cgit v1.2.3 From ad5e5f80ca4ad798d1afbddcae84e04f3a26f0e5 Mon Sep 17 00:00:00 2001 From: gatecat Date: Sun, 9 May 2021 18:28:49 +0100 Subject: mistral: Rename clock buffer primitive Signed-off-by: gatecat --- mistral/globals.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'mistral/globals.cc') diff --git a/mistral/globals.cc b/mistral/globals.cc index 34e569d3..2d1b2ef8 100644 --- a/mistral/globals.cc +++ b/mistral/globals.cc @@ -28,9 +28,10 @@ void Arch::create_clkbuf(int x, int y) for (int z = 0; z < 4; z++) { // For now we only consider the input path from general routing, other inputs like dedicated clock pins are // still a TODO - BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKBUF); + BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA); add_bel_pin(bel, id_A, PORT_IN, get_port(CycloneV::CMUXHG, x, y, -1, CycloneV::CLKIN, z)); add_bel_pin(bel, id_Q, PORT_OUT, get_port(CycloneV::CMUXHG, x, y, z, CycloneV::CLKOUT)); + // TODO: enable pin } } -- cgit v1.2.3 From b29fa1d24c44f7f6454158d27e751203c2d9e099 Mon Sep 17 00:00:00 2001 From: gatecat Date: Fri, 14 May 2021 20:25:41 +0100 Subject: mistral: FF&CLKBUF fixes, part 1 Signed-off-by: gatecat --- mistral/globals.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'mistral/globals.cc') diff --git a/mistral/globals.cc b/mistral/globals.cc index 2d1b2ef8..eee8d0a9 100644 --- a/mistral/globals.cc +++ b/mistral/globals.cc @@ -32,6 +32,7 @@ void Arch::create_clkbuf(int x, int y) add_bel_pin(bel, id_A, PORT_IN, get_port(CycloneV::CMUXHG, x, y, -1, CycloneV::CLKIN, z)); add_bel_pin(bel, id_Q, PORT_OUT, get_port(CycloneV::CMUXHG, x, y, z, CycloneV::CLKOUT)); // TODO: enable pin + bel_data(bel).block_index = z; } } -- cgit v1.2.3 From 4d32c4f2fcb5c5e5ca21100f4473acb2c4cda3b0 Mon Sep 17 00:00:00 2001 From: gatecat Date: Sat, 15 May 2021 09:58:00 +0100 Subject: mistral: Disable global buffers that are currently broken Signed-off-by: gatecat --- mistral/globals.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'mistral/globals.cc') diff --git a/mistral/globals.cc b/mistral/globals.cc index eee8d0a9..97e35518 100644 --- a/mistral/globals.cc +++ b/mistral/globals.cc @@ -26,6 +26,8 @@ NEXTPNR_NAMESPACE_BEGIN void Arch::create_clkbuf(int x, int y) { for (int z = 0; z < 4; z++) { + if (z != 2) + continue; // TODO: why do other Zs not work? // For now we only consider the input path from general routing, other inputs like dedicated clock pins are // still a TODO BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA); -- cgit v1.2.3 From 9221acc9e211766d79d7c7dde5d5fc8bb053354d Mon Sep 17 00:00:00 2001 From: gatecat Date: Sat, 15 May 2021 10:26:27 +0100 Subject: mistral: Fix ENA and ACLR bitstream generation Signed-off-by: gatecat --- mistral/globals.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'mistral/globals.cc') diff --git a/mistral/globals.cc b/mistral/globals.cc index 97e35518..9cbabbca 100644 --- a/mistral/globals.cc +++ b/mistral/globals.cc @@ -26,8 +26,8 @@ NEXTPNR_NAMESPACE_BEGIN void Arch::create_clkbuf(int x, int y) { for (int z = 0; z < 4; z++) { - if (z != 2) - continue; // TODO: why do other Zs not work? + if (z != 2) + continue; // TODO: why do other Zs not work? // For now we only consider the input path from general routing, other inputs like dedicated clock pins are // still a TODO BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA); -- cgit v1.2.3 From 9d7f90dd89d98457e00579615ef9251d0f69f3a4 Mon Sep 17 00:00:00 2001 From: gatecat Date: Sat, 15 May 2021 21:28:48 +0100 Subject: mistral: Add MISTRAL_CLKBUF cell type Signed-off-by: gatecat --- mistral/globals.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'mistral/globals.cc') diff --git a/mistral/globals.cc b/mistral/globals.cc index 9cbabbca..3203893b 100644 --- a/mistral/globals.cc +++ b/mistral/globals.cc @@ -38,4 +38,9 @@ void Arch::create_clkbuf(int x, int y) } } +bool Arch::is_clkbuf_cell(IdString cell_type) const +{ + return cell_type == id_MISTRAL_CLKENA || cell_type == id_MISTRAL_CLKBUF; +} + NEXTPNR_NAMESPACE_END -- cgit v1.2.3