From 510969ab9704865f87c7c0bd09e0185b729feffc Mon Sep 17 00:00:00 2001 From: gatecat Date: Thu, 11 Feb 2021 11:10:32 +0000 Subject: Create machxo2 backend (renamed from generic). Signed-off-by: William D. Jones --- machxo2/examples/simple_timing.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 machxo2/examples/simple_timing.py (limited to 'machxo2/examples/simple_timing.py') diff --git a/machxo2/examples/simple_timing.py b/machxo2/examples/simple_timing.py new file mode 100644 index 00000000..1067b556 --- /dev/null +++ b/machxo2/examples/simple_timing.py @@ -0,0 +1,13 @@ +for cname, cell in ctx.cells: + if cell.type != "GENERIC_SLICE": + continue + if cname in ("$PACKER_GND", "$PACKER_VCC"): + continue + K = int(cell.params["K"]) + ctx.addCellTimingClock(cell=cname, port="CLK") + for i in range(K): + ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", + setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) + ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) + for i in range(K): + ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="F", delay=ctx.getDelayFromNS(0.2)) -- cgit v1.2.3