From fc5e6bec9ab8bf2c25b2b943de4013daf727dfb8 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 12 Nov 2018 13:42:25 +0000
Subject: timing: Add support for clock constraints

Signed-off-by: David Shah <dave@ds0.me>
---
 ice40/arch_pybindings.cc | 4 ++++
 ice40/pack.cc            | 8 ++++++++
 2 files changed, 12 insertions(+)

(limited to 'ice40')

diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc
index f1639ba6..3fafb1f6 100644
--- a/ice40/arch_pybindings.cc
+++ b/ice40/arch_pybindings.cc
@@ -140,6 +140,10 @@ void arch_wrap_python()
                                                                                                              "cells");
     readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls,
                                                                                                           "nets");
+
+    fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>,
+                    pass_through<float>>::def_wrap(ctx_cls, "addClock");
+
     WRAP_RANGE(Bel, conv_to_str<BelId>);
     WRAP_RANGE(Wire, conv_to_str<WireId>);
     WRAP_RANGE(AllPip, conv_to_str<PipId>);
diff --git a/ice40/pack.cc b/ice40/pack.cc
index b9360b74..7a27d505 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -490,6 +490,14 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen
         }
     }
     net->users = keep_users;
+
+    if (net->clkconstr) {
+        glbnet->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+        glbnet->clkconstr->low = net->clkconstr->low;
+        glbnet->clkconstr->high = net->clkconstr->high;
+        glbnet->clkconstr->period = net->clkconstr->period;
+    }
+
     ctx->nets[glbnet->name] = std::move(glbnet);
     ctx->cells[gb->name] = std::move(gb);
 }
-- 
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