From b8a42ff53b1fbb6e03d169d14e58180a750f4cad Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 12 Jul 2018 22:04:13 +0200 Subject: Updates from clang-format Signed-off-by: Clifford Wolf --- ice40/arch.cc | 36 +++++++++++++----------------------- ice40/archdefs.h | 12 ++++++++---- ice40/bitstream.cc | 5 ++--- ice40/chipdb.py | 4 +++- ice40/gfx.cc | 6 +++--- ice40/gfx.h | 3 ++- ice40/main.cc | 10 ++++------ 7 files changed, 35 insertions(+), 41 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index 8650aeff..786bf686 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -19,12 +19,12 @@ #include #include +#include "gfx.h" #include "log.h" #include "nextpnr.h" #include "placer1.h" #include "router1.h" #include "util.h" -#include "gfx.h" NEXTPNR_NAMESPACE_BEGIN @@ -380,10 +380,7 @@ GroupId Arch::getGroupByName(IdString name) const return GroupId(); } -IdString Arch::getGroupName(GroupId group) const -{ - return IdString(); -} +IdString Arch::getGroupName(GroupId group) const { return IdString(); } std::vector Arch::getGroups() const { @@ -448,15 +445,9 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const // ----------------------------------------------------------------------- -bool Arch::place() -{ - return placer1(getCtx()); -} +bool Arch::place() { return placer1(getCtx()); } -bool Arch::route() -{ - return router1(getCtx()); -} +bool Arch::route() { return router1(getCtx()); } // ----------------------------------------------------------------------- @@ -499,8 +490,7 @@ std::vector Arch::getDecalGraphics(DecalId decal) const { std::vector ret; - if (decal.type == DecalId::TYPE_FRAME) - { + if (decal.type == DecalId::TYPE_FRAME) { for (int x = 0; x <= chip_info->width; x++) for (int y = 0; y <= chip_info->height; y++) { GraphicElement el; @@ -512,23 +502,21 @@ std::vector Arch::getDecalGraphics(DecalId decal) const } } - if (decal.type == DecalId::TYPE_WIRE) - { + if (decal.type == DecalId::TYPE_WIRE) { WireId wire; wire.index = decal.index; int n = chip_info->wire_data[wire.index].num_segments; const WireSegmentPOD *p = chip_info->wire_data[wire.index].segments.get(); - GraphicElement::style_t style = wire_to_net.at(wire.index) != IdString() ? - GraphicElement::G_ACTIVE : GraphicElement::G_INACTIVE; + GraphicElement::style_t style = + wire_to_net.at(wire.index) != IdString() ? GraphicElement::G_ACTIVE : GraphicElement::G_INACTIVE; for (int i = 0; i < n; i++) gfxTileWire(ret, p[i].x, p[i].y, GfxTileWireId(p[i].index), style); } - if (decal.type == DecalId::TYPE_BEL) - { + if (decal.type == DecalId::TYPE_BEL) { BelId bel; bel.index = decal.index; @@ -540,8 +528,10 @@ std::vector Arch::getDecalGraphics(DecalId decal) const el.style = bel_to_cell.at(bel.index) != IdString() ? GraphicElement::G_ACTIVE : GraphicElement::G_INACTIVE; el.x1 = chip_info->bel_data[bel.index].x + logic_cell_x1; el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2; - el.y1 = chip_info->bel_data[bel.index].y + logic_cell_y1 + (chip_info->bel_data[bel.index].z) * logic_cell_pitch; - el.y2 = chip_info->bel_data[bel.index].y + logic_cell_y2 + (chip_info->bel_data[bel.index].z) * logic_cell_pitch; + el.y1 = chip_info->bel_data[bel.index].y + logic_cell_y1 + + (chip_info->bel_data[bel.index].z) * logic_cell_pitch; + el.y2 = chip_info->bel_data[bel.index].y + logic_cell_y2 + + (chip_info->bel_data[bel.index].z) * logic_cell_pitch; el.z = 0; ret.push_back(el); diff --git a/ice40/archdefs.h b/ice40/archdefs.h index 62c248c7..3252dabf 100644 --- a/ice40/archdefs.h +++ b/ice40/archdefs.h @@ -111,7 +111,8 @@ struct PipId struct GroupId { - enum : int8_t { + enum : int8_t + { TYPE_NONE, TYPE_FRAME, TYPE_MAIN_SW, @@ -133,7 +134,8 @@ struct GroupId struct DecalId { - enum : int8_t { + enum : int8_t + { TYPE_NONE, TYPE_FRAME, TYPE_BEL, @@ -178,7 +180,8 @@ template <> struct hash : hash template <> struct hash { - std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX GroupId &group) const noexcept { + std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX GroupId &group) const noexcept + { std::size_t seed = 0; boost::hash_combine(seed, hash()(group.type)); boost::hash_combine(seed, hash()(group.x)); @@ -189,7 +192,8 @@ template <> struct hash template <> struct hash { - std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DecalId &decal) const noexcept { + std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DecalId &decal) const noexcept + { std::size_t seed = 0; boost::hash_combine(seed, hash()(decal.type)); boost::hash_combine(seed, hash()(decal.index)); diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 98a7a0e4..a62c6c09 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -341,9 +341,8 @@ void write_asc(const Context *ctx, std::ostream &out) set_config(ti, config.at(y).at(x), "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true); else - set_config(ti, config.at(y).at(x), - "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" + - std::to_string(lc_idx) + "_inmux02_5", + set_config(ti, config.at(y).at(x), "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + + "_LC0" + std::to_string(lc_idx) + "_inmux02_5", true); } } diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 97bc3183..f52a2283 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -73,10 +73,12 @@ with open(args.portspins) as f: with open(args.gfxh) as f: state = 0 for line in f: - if state == 0 and line.startswith("enum GfxTileWireId "): + if state == 0 and line.startswith("enum GfxTileWireId"): state = 1 elif state == 1 and line.startswith("};"): state = 0 + elif state == 1 and line.startswith("{"): + pass elif state == 1: idx = len(gfx_wire_ids) name = line.strip().rstrip(",") diff --git a/ice40/gfx.cc b/ice40/gfx.cc index d6935b7d..f4941750 100644 --- a/ice40/gfx.cc +++ b/ice40/gfx.cc @@ -333,7 +333,7 @@ void gfxTileWire(std::vector &g, int x, int y, GfxTileWireId id, // LC Inputs - if (id >= TILE_WIRE_LUTFF_0_IN_0 && id <= TILE_WIRE_LUTFF_7_IN_3) { + if (id >= TILE_WIRE_LUTFF_0_IN_0 && id <= TILE_WIRE_LUTFF_7_IN_3) { int idx = id - TILE_WIRE_LUTFF_0_IN_0; int z = idx / 4; int input = idx % 4; @@ -354,7 +354,7 @@ void gfxTileWire(std::vector &g, int x, int y, GfxTileWireId id, el.y1 = y1; el.y2 = y1; el.x1 = x + main_swbox_x2; - el.x2 = x + 0.97 + 0.0025 * (7-idx); + el.x2 = x + 0.97 + 0.0025 * (7 - idx); g.push_back(el); el.y1 = y1; @@ -386,7 +386,7 @@ void gfxTileWire(std::vector &g, int x, int y, GfxTileWireId id, el.x1 = el.x2; g.push_back(el); - for (int i = 0; i < 7; i ++) { + for (int i = 0; i < 7; i++) { el.y1 = y + logic_cell_y2 + i * logic_cell_pitch; el.y2 = y + logic_cell_y1 + (i + 1) * logic_cell_pitch; g.push_back(el); diff --git a/ice40/gfx.h b/ice40/gfx.h index aa07c2fa..a65f7683 100644 --- a/ice40/gfx.h +++ b/ice40/gfx.h @@ -40,7 +40,8 @@ const float logic_cell_y1 = 0.05; const float logic_cell_y2 = 0.10; const float logic_cell_pitch = 0.0625; -enum GfxTileWireId { +enum GfxTileWireId +{ TILE_WIRE_GLB2LOCAL_0, TILE_WIRE_GLB2LOCAL_1, TILE_WIRE_GLB2LOCAL_2, diff --git a/ice40/main.cc b/ice40/main.cc index 2427ea6c..5fa58921 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -128,18 +128,16 @@ int main(int argc, char *argv[]) if (vm.count("help") || argc == 1) { help: - std::cout << boost::filesystem::basename(argv[0]) - << " -- Next Generation Place and Route (git " - "sha1 " GIT_COMMIT_HASH_STR ")\n"; + std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git " + "sha1 " GIT_COMMIT_HASH_STR ")\n"; std::cout << "\n"; std::cout << options << "\n"; return argc != 1; } if (vm.count("version")) { - std::cout << boost::filesystem::basename(argv[0]) - << " -- Next Generation Place and Route (git " - "sha1 " GIT_COMMIT_HASH_STR ")\n"; + std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git " + "sha1 " GIT_COMMIT_HASH_STR ")\n"; return 1; } -- cgit v1.2.3