From c27c96f4f0ec66d13bea7d7cdea25fbeb2e189b7 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 20 Jun 2018 20:12:23 +0200 Subject: place_sa: Improvements including supporting force and ordering consistency Signed-off-by: David Shah --- ice40/pack.cc | 4 ++-- ice40/picorv32_arachne.sh | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'ice40') diff --git a/ice40/pack.cc b/ice40/pack.cc index 19f1e7bc..853f510e 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -244,8 +244,8 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, CellInfo *uc = user.cell; log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx)); - if (is_lut(ctx, uc) && (user.port.str(ctx).at(0) == 'I') && - !constval) { + if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && + (user.port.str(ctx).at(0) == 'I') && !constval) { uc->ports[user.port].net = nullptr; } else { uc->ports[user.port].net = constnet; diff --git a/ice40/picorv32_arachne.sh b/ice40/picorv32_arachne.sh index 00cfe6a4..b3960fdc 100755 --- a/ice40/picorv32_arachne.sh +++ b/ice40/picorv32_arachne.sh @@ -3,7 +3,7 @@ set -ex rm -f picorv32.v wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v yosys -p 'synth_ice40 -nocarry -blif picorv32.blif -top top' picorv32.v picorv32_top.v -arachne-pnr -d 8k --post-place-blif picorv32_place.blif picorv32.blif +arachne-pnr -d 8k --post-place-blif picorv32_place.blif picorv32.blif -o picorv32_arachne_all.asc yosys -p "read_blif -wideports picorv32_place.blif; read_verilog -lib +/ice40/cells_sim.v; write_json picorv32_place.json" ./transform_arachne_loc.py picorv32_place.json > picorv32_place_nx.json -../nextpnr-ice40 --hx8k --asc picorv32.asc --json picorv32_place_nx.json +../nextpnr-ice40 --hx8k --asc picorv32_ar_placed.asc --json picorv32_place_nx.json --force -- cgit v1.2.3 From 56ed679f831f703ad2f170713e0b127a97da40b3 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 21 Jun 2018 11:59:20 +0200 Subject: Add frequency setting and fix slack calculation Signed-off-by: David Shah --- ice40/main.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'ice40') diff --git a/ice40/main.cc b/ice40/main.cc index 8143a902..fcf112e6 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -93,6 +93,8 @@ int main(int argc, char *argv[]) options.add_options()("hx1k", "set device type to iCE40HX1K"); options.add_options()("hx8k", "set device type to iCE40HX8K"); options.add_options()("up5k", "set device type to iCE40UP5K"); + options.add_options()("freq", po::value(), + "set target frequency for design in MHz"); options.add_options()("package", po::value(), "set device package"); po::positional_options_description pos; @@ -286,7 +288,10 @@ int main(int argc, char *argv[]) if (!pack_design(&ctx) && !ctx.force) log_error("Packing design failed.\n"); - assign_budget(&ctx, 50e6); + double freq = 50e6; + if (vm.count("freq")) + freq = vm["freq"].as() * 1e6; + assign_budget(&ctx, freq); print_utilisation(&ctx); if (!vm.count("pack-only")) { -- cgit v1.2.3 From 693c34ad0646aac1bb766e783eb94d710f8ff72b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Jun 2018 14:08:45 +0200 Subject: Improvements in router Signed-off-by: Clifford Wolf --- ice40/arch.h | 3 ++- ice40/main.cc | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'ice40') diff --git a/ice40/arch.h b/ice40/arch.h index 85fb9fc0..4896736b 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -755,7 +755,8 @@ struct Arch : BaseCtx void estimatePosition(BelId bel, int &x, int &y, bool &gb) const; delay_t estimateDelay(WireId src, WireId dst) const; - delay_t getDelayEpsilon() const { return 10; } + delay_t getDelayEpsilon() const { return 20; } + delay_t getRipupDelayPenalty() const { return 200; } float getDelayNS(delay_t v) const { return v * 0.001; } // ------------------------------------------------- diff --git a/ice40/main.cc b/ice40/main.cc index fcf112e6..e86cd5b1 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -69,6 +69,7 @@ int main(int argc, char *argv[]) po::options_description options("Allowed options"); options.add_options()("help,h", "show help"); options.add_options()("verbose,v", "verbose output"); + options.add_options()("debug", "debug output"); options.add_options()("force,f", "keep running after errors"); options.add_options()("gui", "start gui"); options.add_options()("svg", "dump SVG file"); @@ -201,6 +202,11 @@ int main(int argc, char *argv[]) ctx.verbose = true; } + if (vm.count("debug")) { + ctx.verbose = true; + ctx.debug = true; + } + if (vm.count("force")) { ctx.force = true; } -- cgit v1.2.3 From 993f6ef7d31ceee5fc71a99fcec19b521694e4f3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Jun 2018 14:09:50 +0200 Subject: Improve log messages, move many messages to verbose mode Signed-off-by: Clifford Wolf --- ice40/pack.cc | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) (limited to 'ice40') diff --git a/ice40/pack.cc b/ice40/pack.cc index 853f510e..8a6f1c45 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -36,8 +36,9 @@ static void pack_lut_lutffs(Context *ctx) std::vector new_cells; for (auto cell : ctx->cells) { CellInfo *ci = cell.second; - log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), - ci->type.c_str(ctx)); + if (ctx->verbose) + log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), + ci->type.c_str(ctx)); if (is_lut(ctx, ci)) { CellInfo *packed = create_ice_cell(ctx, "ICESTORM_LC", ci->name.str(ctx) + "_LC"); @@ -45,8 +46,9 @@ static void pack_lut_lutffs(Context *ctx) std::inserter(packed->attrs, packed->attrs.begin())); packed_cells.insert(ci->name); new_cells.push_back(packed); - log_info("packed cell %s into %s\n", ci->name.c_str(ctx), - packed->name.c_str(ctx)); + if (ctx->verbose) + log_info("packed cell %s into %s\n", ci->name.c_str(ctx), + packed->name.c_str(ctx)); // See if we can pack into a DFF // TODO: LUT cascade NetInfo *o = ci->ports.at(ctx->id("O")).net; @@ -54,7 +56,8 @@ static void pack_lut_lutffs(Context *ctx) auto lut_bel = ci->attrs.find(ctx->id("BEL")); bool packed_dff = false; if (dff) { - log_info("found attached dff %s\n", dff->name.c_str(ctx)); + if (ctx->verbose) + log_info("found attached dff %s\n", dff->name.c_str(ctx)); auto dff_bel = dff->attrs.find(ctx->id("BEL")); if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) { @@ -66,8 +69,9 @@ static void pack_lut_lutffs(Context *ctx) if (dff_bel != dff->attrs.end()) packed->attrs[ctx->id("BEL")] = dff_bel->second; packed_cells.insert(dff->name); - log_info("packed cell %s into %s\n", dff->name.c_str(ctx), - packed->name.c_str(ctx)); + if (ctx->verbose) + log_info("packed cell %s into %s\n", + dff->name.c_str(ctx), packed->name.c_str(ctx)); packed_dff = true; } } @@ -99,8 +103,9 @@ static void pack_nonlut_ffs(Context *ctx) ci->name.str(ctx) + "_DFFLC"); std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin())); - log_info("packed cell %s into %s\n", ci->name.c_str(ctx), - packed->name.c_str(ctx)); + if (ctx->verbose) + log_info("packed cell %s into %s\n", ci->name.c_str(ctx), + packed->name.c_str(ctx)); packed_cells.insert(ci->name); new_cells.push_back(packed); dff_to_lc(ctx, ci, packed, true); @@ -242,8 +247,9 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, for (auto user : orig->users) { if (user.cell != nullptr) { CellInfo *uc = user.cell; - log_info("%s user %s\n", orig->name.c_str(ctx), - uc->name.c_str(ctx)); + if (ctx->verbose) + log_info("%s user %s\n", orig->name.c_str(ctx), + uc->name.c_str(ctx)); if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) { uc->ports[user.port].net = nullptr; -- cgit v1.2.3 From a29bfc788eba9f11f1e0cd3d62a32c3894cddf49 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Jun 2018 15:47:41 +0200 Subject: Add ctx->checksum(), slightly improve log messages Signed-off-by: Clifford Wolf --- ice40/arch.h | 16 ++++++++++++++++ ice40/pack.cc | 2 ++ 2 files changed, 18 insertions(+) (limited to 'ice40') diff --git a/ice40/arch.h b/ice40/arch.h index 4896736b..7778e1c5 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -515,6 +515,11 @@ struct Arch : BaseCtx return id(chip_info->bel_data[bel.index].name.get()); } + uint32_t getBelChecksum(BelId bel) const + { + return bel.index; + } + void bindBel(BelId bel, IdString cell) { assert(bel != BelId()); @@ -607,6 +612,11 @@ struct Arch : BaseCtx return id(chip_info->wire_data[wire.index].name.get()); } + uint32_t getWireChecksum(WireId wire) const + { + return wire.index; + } + void bindWire(WireId wire, IdString net) { assert(wire != WireId()); @@ -646,6 +656,11 @@ struct Arch : BaseCtx PipId getPipByName(IdString name) const; IdString getPipName(PipId pip) const; + uint32_t getPipChecksum(PipId pip) const + { + return pip.index; + } + void bindPip(PipId pip, IdString net) { assert(pip != PipId()); @@ -758,6 +773,7 @@ struct Arch : BaseCtx delay_t getDelayEpsilon() const { return 20; } delay_t getRipupDelayPenalty() const { return 200; } float getDelayNS(delay_t v) const { return v * 0.001; } + uint32_t getDelayChecksum(delay_t v) const { return v; } // ------------------------------------------------- diff --git a/ice40/pack.cc b/ice40/pack.cc index 8a6f1c45..7fcf2750 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -487,12 +487,14 @@ static void promote_globals(Context *ctx) // Main pack function bool pack_design(Context *ctx) { + log_break(); pack_constants(ctx); promote_globals(ctx); pack_io(ctx); pack_lut_lutffs(ctx); pack_nonlut_ffs(ctx); pack_ram(ctx); + log_info("Checksum: 0x%08x\n", ctx->checksum()); return true; } -- cgit v1.2.3 From 4fefdbd57c52d6373456bd379e3e54df770e1945 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Jun 2018 16:16:58 +0200 Subject: Cleanup parse_json_file API, some other cleanups Signed-off-by: Clifford Wolf --- ice40/main.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ice40') diff --git a/ice40/main.cc b/ice40/main.cc index e86cd5b1..76c059b8 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -283,7 +283,7 @@ int main(int argc, char *argv[]) if (vm.count("json")) { std::string filename = vm["json"].as(); - std::istream *f = new std::ifstream(filename); + std::ifstream f(filename); parse_json_file(f, filename, &ctx); -- cgit v1.2.3 From 54549d36e911aac8d0b0a2eea6074654c06c9717 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 21 Jun 2018 17:44:18 +0200 Subject: log_error now trows exception, main is covering catch --- ice40/main.cc | 472 ++++++++++++++++++++++++++++++---------------------------- 1 file changed, 241 insertions(+), 231 deletions(-) (limited to 'ice40') diff --git a/ice40/main.cc b/ice40/main.cc index 76c059b8..67d71dc1 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -60,276 +60,286 @@ void svg_dump_el(const GraphicElement &el) int main(int argc, char *argv[]) { - namespace po = boost::program_options; - int rc = 0; - std::string str; - - log_files.push_back(stdout); - - po::options_description options("Allowed options"); - options.add_options()("help,h", "show help"); - options.add_options()("verbose,v", "verbose output"); - options.add_options()("debug", "debug output"); - options.add_options()("force,f", "keep running after errors"); - options.add_options()("gui", "start gui"); - options.add_options()("svg", "dump SVG file"); - options.add_options()("pack-only", - "pack design only without placement or routing"); - - options.add_options()("run", po::value>(), - "python file to execute"); - options.add_options()("json", po::value(), - "JSON design file to ingest"); - options.add_options()("pcf", po::value(), - "PCF constraints file to ingest"); - options.add_options()("asc", po::value(), - "asc bitstream file to write"); - options.add_options()("seed", po::value(), - "seed value for random number generator"); - options.add_options()("version,V", "show version"); - options.add_options()("tmfuzz", "run path delay estimate fuzzer"); - options.add_options()("lp384", "set device type to iCE40LP384"); - options.add_options()("lp1k", "set device type to iCE40LP1K"); - options.add_options()("lp8k", "set device type to iCE40LP8K"); - options.add_options()("hx1k", "set device type to iCE40HX1K"); - options.add_options()("hx8k", "set device type to iCE40HX8K"); - options.add_options()("up5k", "set device type to iCE40UP5K"); - options.add_options()("freq", po::value(), - "set target frequency for design in MHz"); - options.add_options()("package", po::value(), - "set device package"); - po::positional_options_description pos; - pos.add("run", -1); - - po::variables_map vm; try { - po::parsed_options parsed = po::command_line_parser(argc, argv) - .options(options) - .positional(pos) - .run(); - - po::store(parsed, vm); - - po::notify(vm); - } + namespace po = boost::program_options; + int rc = 0; + std::string str; + + log_files.push_back(stdout); + + po::options_description options("Allowed options"); + options.add_options()("help,h", "show help"); + options.add_options()("verbose,v", "verbose output"); + options.add_options()("debug", "debug output"); + options.add_options()("force,f", "keep running after errors"); + options.add_options()("gui", "start gui"); + options.add_options()("svg", "dump SVG file"); + options.add_options()("pack-only", + "pack design only without placement or routing"); + + options.add_options()("run", po::value>(), + "python file to execute"); + options.add_options()("json", po::value(), + "JSON design file to ingest"); + options.add_options()("pcf", po::value(), + "PCF constraints file to ingest"); + options.add_options()("asc", po::value(), + "asc bitstream file to write"); + options.add_options()("seed", po::value(), + "seed value for random number generator"); + options.add_options()("version,V", "show version"); + options.add_options()("tmfuzz", "run path delay estimate fuzzer"); + options.add_options()("lp384", "set device type to iCE40LP384"); + options.add_options()("lp1k", "set device type to iCE40LP1K"); + options.add_options()("lp8k", "set device type to iCE40LP8K"); + options.add_options()("hx1k", "set device type to iCE40HX1K"); + options.add_options()("hx8k", "set device type to iCE40HX8K"); + options.add_options()("up5k", "set device type to iCE40UP5K"); + options.add_options()("freq", po::value(), + "set target frequency for design in MHz"); + options.add_options()("package", po::value(), + "set device package"); + po::positional_options_description pos; + pos.add("run", -1); + + po::variables_map vm; + try { + po::parsed_options parsed = po::command_line_parser(argc, argv) + .options(options) + .positional(pos) + .run(); + + po::store(parsed, vm); + + po::notify(vm); + } - catch (std::exception &e) { - std::cout << e.what() << "\n"; - return 1; - } + catch (std::exception &e) { + std::cout << e.what() << "\n"; + return 1; + } - if (vm.count("help") || argc == 1) { - help: - std::cout << boost::filesystem::basename(argv[0]) - << " -- Next Generation Place and Route (git " - "sha1 " GIT_COMMIT_HASH_STR ")\n"; - std::cout << "\n"; - std::cout << options << "\n"; - return argc != 1; - } + if (vm.count("help") || argc == 1) { + help: + std::cout << boost::filesystem::basename(argv[0]) + << " -- Next Generation Place and Route (git " + "sha1 " GIT_COMMIT_HASH_STR ")\n"; + std::cout << "\n"; + std::cout << options << "\n"; + return argc != 1; + } - if (vm.count("version")) { - std::cout << boost::filesystem::basename(argv[0]) - << " -- Next Generation Place and Route (git " - "sha1 " GIT_COMMIT_HASH_STR ")\n"; - return 1; - } + if (vm.count("version")) { + std::cout << boost::filesystem::basename(argv[0]) + << " -- Next Generation Place and Route (git " + "sha1 " GIT_COMMIT_HASH_STR ")\n"; + return 1; + } - ArchArgs chipArgs; + ArchArgs chipArgs; - if (vm.count("lp384")) { - if (chipArgs.type != ArchArgs::NONE) - goto help; - chipArgs.type = ArchArgs::LP384; - chipArgs.package = "qn32"; - } + if (vm.count("lp384")) { + if (chipArgs.type != ArchArgs::NONE) + goto help; + chipArgs.type = ArchArgs::LP384; + chipArgs.package = "qn32"; + } - if (vm.count("lp1k")) { - if (chipArgs.type != ArchArgs::NONE) - goto help; - chipArgs.type = ArchArgs::LP1K; - chipArgs.package = "tq144"; - } + if (vm.count("lp1k")) { + if (chipArgs.type != ArchArgs::NONE) + goto help; + chipArgs.type = ArchArgs::LP1K; + chipArgs.package = "tq144"; + } - if (vm.count("lp8k")) { - if (chipArgs.type != ArchArgs::NONE) - goto help; - chipArgs.type = ArchArgs::LP8K; - chipArgs.package = "ct256"; - } + if (vm.count("lp8k")) { + if (chipArgs.type != ArchArgs::NONE) + goto help; + chipArgs.type = ArchArgs::LP8K; + chipArgs.package = "ct256"; + } - if (vm.count("hx1k")) { - if (chipArgs.type != ArchArgs::NONE) - goto help; - chipArgs.type = ArchArgs::HX1K; - chipArgs.package = "tq144"; - } + if (vm.count("hx1k")) { + if (chipArgs.type != ArchArgs::NONE) + goto help; + chipArgs.type = ArchArgs::HX1K; + chipArgs.package = "tq144"; + } - if (vm.count("hx8k")) { - if (chipArgs.type != ArchArgs::NONE) - goto help; - chipArgs.type = ArchArgs::HX8K; - chipArgs.package = "ct256"; - } + if (vm.count("hx8k")) { + if (chipArgs.type != ArchArgs::NONE) + goto help; + chipArgs.type = ArchArgs::HX8K; + chipArgs.package = "ct256"; + } - if (vm.count("up5k")) { - if (chipArgs.type != ArchArgs::NONE) - goto help; - chipArgs.type = ArchArgs::UP5K; - chipArgs.package = "sg48"; - } + if (vm.count("up5k")) { + if (chipArgs.type != ArchArgs::NONE) + goto help; + chipArgs.type = ArchArgs::UP5K; + chipArgs.package = "sg48"; + } - if (chipArgs.type == ArchArgs::NONE) { - chipArgs.type = ArchArgs::HX1K; - chipArgs.package = "tq144"; - } + if (chipArgs.type == ArchArgs::NONE) { + chipArgs.type = ArchArgs::HX1K; + chipArgs.package = "tq144"; + } #ifdef ICE40_HX1K_ONLY - if (chipArgs.type != ArchArgs::HX1K) { - std::cout << "This version of nextpnr-ice40 is built with HX1K-support " - "only.\n"; - return 1; - } + if (chipArgs.type != ArchArgs::HX1K) { + std::cout << "This version of nextpnr-ice40 is built with " + "HX1K-support " + "only.\n"; + return 1; + } #endif - if (vm.count("package")) - chipArgs.package = vm["package"].as(); + if (vm.count("package")) + chipArgs.package = vm["package"].as(); - Context ctx(chipArgs); - init_python(argv[0]); - python_export_global("ctx", ctx); + Context ctx(chipArgs); + init_python(argv[0]); + python_export_global("ctx", ctx); - if (vm.count("verbose")) { - ctx.verbose = true; - } - - if (vm.count("debug")) { - ctx.verbose = true; - ctx.debug = true; - } - - if (vm.count("force")) { - ctx.force = true; - } + if (vm.count("verbose")) { + ctx.verbose = true; + } - if (vm.count("seed")) { - ctx.rngseed(vm["seed"].as()); - } + if (vm.count("debug")) { + ctx.verbose = true; + ctx.debug = true; + } - if (vm.count("svg")) { - std::cout << "\n"; - for (auto bel : ctx.getBels()) { - std::cout << "\n"; - for (auto &el : ctx.getBelGraphics(bel)) - svg_dump_el(el); + if (vm.count("force")) { + ctx.force = true; } - std::cout << "\n"; - for (auto &el : ctx.getFrameGraphics()) - svg_dump_el(el); - std::cout << "\n"; - } - if (vm.count("tmfuzz")) { - std::vector src_wires, dst_wires; + if (vm.count("seed")) { + ctx.rngseed(vm["seed"].as()); + } - /*for (auto w : ctx.getWires()) - src_wires.push_back(w);*/ - for (auto b : ctx.getBels()) { - if (ctx.getBelType(b) == TYPE_ICESTORM_LC) { - src_wires.push_back(ctx.getWireBelPin(b, PIN_O)); - } - if (ctx.getBelType(b) == TYPE_SB_IO) { - src_wires.push_back(ctx.getWireBelPin(b, PIN_D_IN_0)); + if (vm.count("svg")) { + std::cout << "\n"; + for (auto bel : ctx.getBels()) { + std::cout << "\n"; + for (auto &el : ctx.getBelGraphics(bel)) + svg_dump_el(el); } + std::cout << "\n"; + for (auto &el : ctx.getFrameGraphics()) + svg_dump_el(el); + std::cout << "\n"; } - for (auto b : ctx.getBels()) { - if (ctx.getBelType(b) == TYPE_ICESTORM_LC) { - dst_wires.push_back(ctx.getWireBelPin(b, PIN_I0)); - dst_wires.push_back(ctx.getWireBelPin(b, PIN_I1)); - dst_wires.push_back(ctx.getWireBelPin(b, PIN_I2)); - dst_wires.push_back(ctx.getWireBelPin(b, PIN_I3)); - dst_wires.push_back(ctx.getWireBelPin(b, PIN_CEN)); - dst_wires.push_back(ctx.getWireBelPin(b, PIN_CIN)); + if (vm.count("tmfuzz")) { + std::vector src_wires, dst_wires; + + /*for (auto w : ctx.getWires()) + src_wires.push_back(w);*/ + for (auto b : ctx.getBels()) { + if (ctx.getBelType(b) == TYPE_ICESTORM_LC) { + src_wires.push_back(ctx.getWireBelPin(b, PIN_O)); + } + if (ctx.getBelType(b) == TYPE_SB_IO) { + src_wires.push_back(ctx.getWireBelPin(b, PIN_D_IN_0)); + } } - if (ctx.getBelType(b) == TYPE_SB_IO) { - dst_wires.push_back(ctx.getWireBelPin(b, PIN_D_OUT_0)); - dst_wires.push_back(ctx.getWireBelPin(b, PIN_OUTPUT_ENABLE)); + + for (auto b : ctx.getBels()) { + if (ctx.getBelType(b) == TYPE_ICESTORM_LC) { + dst_wires.push_back(ctx.getWireBelPin(b, PIN_I0)); + dst_wires.push_back(ctx.getWireBelPin(b, PIN_I1)); + dst_wires.push_back(ctx.getWireBelPin(b, PIN_I2)); + dst_wires.push_back(ctx.getWireBelPin(b, PIN_I3)); + dst_wires.push_back(ctx.getWireBelPin(b, PIN_CEN)); + dst_wires.push_back(ctx.getWireBelPin(b, PIN_CIN)); + } + if (ctx.getBelType(b) == TYPE_SB_IO) { + dst_wires.push_back(ctx.getWireBelPin(b, PIN_D_OUT_0)); + dst_wires.push_back( + ctx.getWireBelPin(b, PIN_OUTPUT_ENABLE)); + } } - } - ctx.shuffle(src_wires); - ctx.shuffle(dst_wires); - - for (int i = 0; i < int(src_wires.size()) && i < int(dst_wires.size()); - i++) { - delay_t actual_delay; - WireId src = src_wires[i], dst = dst_wires[i]; - if (!get_actual_route_delay(&ctx, src, dst, actual_delay)) - continue; - printf("%s %s %.3f %.3f %d %d %d %d %d %d\n", - ctx.getWireName(src).c_str(&ctx), - ctx.getWireName(dst).c_str(&ctx), - ctx.getDelayNS(actual_delay), - ctx.getDelayNS(ctx.estimateDelay(src, dst)), - ctx.chip_info->wire_data[src.index].x, - ctx.chip_info->wire_data[src.index].y, - ctx.chip_info->wire_data[src.index].type, - ctx.chip_info->wire_data[dst.index].x, - ctx.chip_info->wire_data[dst.index].y, - ctx.chip_info->wire_data[dst.index].type); + ctx.shuffle(src_wires); + ctx.shuffle(dst_wires); + + for (int i = 0; + i < int(src_wires.size()) && i < int(dst_wires.size()); i++) { + delay_t actual_delay; + WireId src = src_wires[i], dst = dst_wires[i]; + if (!get_actual_route_delay(&ctx, src, dst, actual_delay)) + continue; + printf("%s %s %.3f %.3f %d %d %d %d %d %d\n", + ctx.getWireName(src).c_str(&ctx), + ctx.getWireName(dst).c_str(&ctx), + ctx.getDelayNS(actual_delay), + ctx.getDelayNS(ctx.estimateDelay(src, dst)), + ctx.chip_info->wire_data[src.index].x, + ctx.chip_info->wire_data[src.index].y, + ctx.chip_info->wire_data[src.index].type, + ctx.chip_info->wire_data[dst.index].x, + ctx.chip_info->wire_data[dst.index].y, + ctx.chip_info->wire_data[dst.index].type); + } } - } - if (vm.count("json")) { - std::string filename = vm["json"].as(); - std::ifstream f(filename); + if (vm.count("json")) { + std::string filename = vm["json"].as(); + std::ifstream f(filename); + parse_json_file(f, filename, &ctx); - parse_json_file(f, filename, &ctx); + if (vm.count("pcf")) { + std::ifstream pcf(vm["pcf"].as()); + apply_pcf(&ctx, pcf); + } - if (vm.count("pcf")) { - std::ifstream pcf(vm["pcf"].as()); - apply_pcf(&ctx, pcf); + if (!pack_design(&ctx) && !ctx.force) + log_error("Packing design failed.\n"); + double freq = 50e6; + if (vm.count("freq")) + freq = vm["freq"].as() * 1e6; + assign_budget(&ctx, freq); + print_utilisation(&ctx); + + if (!vm.count("pack-only")) { + if (!place_design_sa(&ctx) && !ctx.force) + log_error("Placing design failed.\n"); + if (!route_design(&ctx) && !ctx.force) + log_error("Routing design failed.\n"); + } } - if (!pack_design(&ctx) && !ctx.force) - log_error("Packing design failed.\n"); - double freq = 50e6; - if (vm.count("freq")) - freq = vm["freq"].as() * 1e6; - assign_budget(&ctx, freq); - print_utilisation(&ctx); - - if (!vm.count("pack-only")) { - if (!place_design_sa(&ctx) && !ctx.force) - log_error("Placing design failed.\n"); - if (!route_design(&ctx) && !ctx.force) - log_error("Routing design failed.\n"); + if (vm.count("asc")) { + std::string filename = vm["asc"].as(); + std::ofstream f(filename); + write_asc(&ctx, f); } - } - if (vm.count("asc")) { - std::string filename = vm["asc"].as(); - std::ofstream f(filename); - write_asc(&ctx, f); - } - - if (vm.count("run")) { - std::vector files = - vm["run"].as>(); - for (auto filename : files) - execute_python_file(filename.c_str()); - } + if (vm.count("run")) { + std::vector files = + vm["run"].as>(); + for (auto filename : files) + execute_python_file(filename.c_str()); + } - if (vm.count("gui")) { - QApplication a(argc, argv); - MainWindow w(&ctx); - w.show(); + if (vm.count("gui")) { + QApplication a(argc, argv); + MainWindow w(&ctx); + w.show(); - rc = a.exec(); + rc = a.exec(); + } + deinit_python(); + return rc; + } catch (log_execution_error_exception) { +#if defined(_MSC_VER) + _exit(EXIT_FAILURE); +#else + _Exit(EXIT_FAILURE); +#endif } - deinit_python(); - return rc; } #endif -- cgit v1.2.3 From 8fac26c2b795865098b1ba16152cd1c510133f29 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 21 Jun 2018 17:56:45 +0200 Subject: Fixed return codes for packer, placer and router --- ice40/pack.cc | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'ice40') diff --git a/ice40/pack.cc b/ice40/pack.cc index 7fcf2750..9258014e 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -487,15 +487,19 @@ static void promote_globals(Context *ctx) // Main pack function bool pack_design(Context *ctx) { - log_break(); - pack_constants(ctx); - promote_globals(ctx); - pack_io(ctx); - pack_lut_lutffs(ctx); - pack_nonlut_ffs(ctx); - pack_ram(ctx); - log_info("Checksum: 0x%08x\n", ctx->checksum()); - return true; + try { + log_break(); + pack_constants(ctx); + promote_globals(ctx); + pack_io(ctx); + pack_lut_lutffs(ctx); + pack_nonlut_ffs(ctx); + pack_ram(ctx); + log_info("Checksum: 0x%08x\n", ctx->checksum()); + return true; + } catch (log_execution_error_exception) { + return false; + } } NEXTPNR_NAMESPACE_END -- cgit v1.2.3 From c33a039ac388bfcb5e068a04a7cb1b05ebec7d7f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 21 Jun 2018 18:08:28 +0200 Subject: Added return code to json parsing and pcf reading --- ice40/main.cc | 6 +++-- ice40/pcf.cc | 75 ++++++++++++++++++++++++++++++++--------------------------- ice40/pcf.h | 2 +- 3 files changed, 46 insertions(+), 37 deletions(-) (limited to 'ice40') diff --git a/ice40/main.cc b/ice40/main.cc index 67d71dc1..067637e8 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -288,11 +288,13 @@ int main(int argc, char *argv[]) if (vm.count("json")) { std::string filename = vm["json"].as(); std::ifstream f(filename); - parse_json_file(f, filename, &ctx); + if (!parse_json_file(f, filename, &ctx)) + log_error("Loading design failed.\n"); if (vm.count("pcf")) { std::ifstream pcf(vm["pcf"].as()); - apply_pcf(&ctx, pcf); + if (!apply_pcf(&ctx, pcf)) + log_error("Loading PCF failed.\n"); } if (!pack_design(&ctx) && !ctx.force) diff --git a/ice40/pcf.cc b/ice40/pcf.cc index 756aba4a..87d27ff1 100644 --- a/ice40/pcf.cc +++ b/ice40/pcf.cc @@ -27,44 +27,51 @@ NEXTPNR_NAMESPACE_BEGIN // Read a w // Apply PCF constraints to a pre-packing design -void apply_pcf(Context *ctx, std::istream &in) +bool apply_pcf(Context *ctx, std::istream &in) { - if (!in) - log_error("failed to open PCF file"); - std::string line; - while (std::getline(in, line)) { - size_t cstart = line.find("#"); - if (cstart != std::string::npos) - line = line.substr(0, cstart); - std::stringstream ss(line); - std::vector words; - std::string tmp; - while (ss >> tmp) - words.push_back(tmp); - if (words.size() == 0) - continue; - std::string cmd = words.at(0); - if (cmd == "set_io") { - size_t args_end = 1; - while (args_end < words.size() && words.at(args_end).at(0) == '-') - args_end++; - std::string cell = words.at(args_end); - std::string pin = words.at(args_end + 1); - auto fnd_cell = ctx->cells.find(cell); - if (fnd_cell == ctx->cells.end()) { - log_warning("unmatched pcf constraint %s\n", cell.c_str()); + try { + if (!in) + log_error("failed to open PCF file"); + std::string line; + while (std::getline(in, line)) { + size_t cstart = line.find("#"); + if (cstart != std::string::npos) + line = line.substr(0, cstart); + std::stringstream ss(line); + std::vector words; + std::string tmp; + while (ss >> tmp) + words.push_back(tmp); + if (words.size() == 0) + continue; + std::string cmd = words.at(0); + if (cmd == "set_io") { + size_t args_end = 1; + while (args_end < words.size() && + words.at(args_end).at(0) == '-') + args_end++; + std::string cell = words.at(args_end); + std::string pin = words.at(args_end + 1); + auto fnd_cell = ctx->cells.find(cell); + if (fnd_cell == ctx->cells.end()) { + log_warning("unmatched pcf constraint %s\n", cell.c_str()); + } else { + BelId pin_bel = ctx->getPackagePinBel(pin); + if (pin_bel == BelId()) + log_error("package does not have a pin named %s\n", + pin.c_str()); + fnd_cell->second->attrs["BEL"] = + ctx->getBelName(pin_bel).str(); + log_info("constrained '%s' to bel '%s'\n", cell.c_str(), + fnd_cell->second->attrs["BEL"].c_str()); + } } else { - BelId pin_bel = ctx->getPackagePinBel(pin); - if (pin_bel == BelId()) - log_error("package does not have a pin named %s\n", - pin.c_str()); - fnd_cell->second->attrs["BEL"] = ctx->getBelName(pin_bel).str(); - log_info("constrained '%s' to bel '%s'\n", cell.c_str(), - fnd_cell->second->attrs["BEL"].c_str()); + log_error("unsupported pcf command '%s'\n", cmd.c_str()); } - } else { - log_error("unsupported pcf command '%s'\n", cmd.c_str()); } + return true; + } catch (log_execution_error_exception) { + return false; } } diff --git a/ice40/pcf.h b/ice40/pcf.h index e0816075..b86a7609 100644 --- a/ice40/pcf.h +++ b/ice40/pcf.h @@ -27,7 +27,7 @@ NEXTPNR_NAMESPACE_BEGIN // Apply PCF constraints to a pre-packing design -void apply_pcf(Context *ctx, std::istream &in); +bool apply_pcf(Context *ctx, std::istream &in); NEXTPNR_NAMESPACE_END -- cgit v1.2.3 From 2c98231f88cd145267048b32a5ce0e4deadc2716 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Jun 2018 19:36:20 +0200 Subject: Updates from clangformat Signed-off-by: Clifford Wolf --- ice40/arch.h | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.h b/ice40/arch.h index 7778e1c5..f3a46f5c 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -515,10 +515,7 @@ struct Arch : BaseCtx return id(chip_info->bel_data[bel.index].name.get()); } - uint32_t getBelChecksum(BelId bel) const - { - return bel.index; - } + uint32_t getBelChecksum(BelId bel) const { return bel.index; } void bindBel(BelId bel, IdString cell) { @@ -612,10 +609,7 @@ struct Arch : BaseCtx return id(chip_info->wire_data[wire.index].name.get()); } - uint32_t getWireChecksum(WireId wire) const - { - return wire.index; - } + uint32_t getWireChecksum(WireId wire) const { return wire.index; } void bindWire(WireId wire, IdString net) { @@ -656,10 +650,7 @@ struct Arch : BaseCtx PipId getPipByName(IdString name) const; IdString getPipName(PipId pip) const; - uint32_t getPipChecksum(PipId pip) const - { - return pip.index; - } + uint32_t getPipChecksum(PipId pip) const { return pip.index; } void bindPip(PipId pip, IdString net) { -- cgit v1.2.3 From 71176ac5384c696dde1d5601ea1beb5c46f281c6 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 22 Jun 2018 12:34:42 +0200 Subject: Fixing 5k bitstream gen and place heuristics Signed-off-by: David Shah --- ice40/bitstream.cc | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'ice40') diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 8754fef7..e722cea4 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -229,6 +229,16 @@ void write_asc(const Context *ctx, std::ostream &out) set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup); } + + if (ctx->args.type == ArchArgs::UP5K) { + if (iez == 0) { + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39", + !pullup); + } else if (iez == 1) { + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_35", + !pullup); + } + } } else if (cell.second->type == ctx->id("SB_GB")) { // no cell config bits } else if (cell.second->type == ctx->id("ICESTORM_RAM")) { @@ -312,7 +322,8 @@ void write_asc(const Context *ctx, std::ostream &out) ctx->args.type == ArchArgs::HX8K) { setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25); } else if (ctx->args.type == ArchArgs::UP5K) { - if (tile == TILE_LOGIC) { + if (tile == TILE_LOGIC || tile == TILE_RAMB || + tile == TILE_RAMT) { setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 || y == 26 || y == 27); } else { -- cgit v1.2.3 From 63baa10032ecf301523e4cb1fca198d8a8b79e23 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 22 Jun 2018 12:57:22 +0200 Subject: ice40: Make the packer deterministic Signed-off-by: David Shah --- ice40/pack.cc | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'ice40') diff --git a/ice40/pack.cc b/ice40/pack.cc index 9258014e..35cef8b8 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -24,6 +24,7 @@ #include "cells.h" #include "design_utils.h" #include "log.h" +#include "util.h" NEXTPNR_NAMESPACE_BEGIN @@ -34,7 +35,7 @@ static void pack_lut_lutffs(Context *ctx) std::unordered_set packed_cells; std::vector new_cells; - for (auto cell : ctx->cells) { + for (auto cell : sorted(ctx->cells)) { CellInfo *ci = cell.second; if (ctx->verbose) log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), @@ -96,7 +97,7 @@ static void pack_nonlut_ffs(Context *ctx) std::unordered_set packed_cells; std::vector new_cells; - for (auto cell : ctx->cells) { + for (auto cell : sorted(ctx->cells)) { CellInfo *ci = cell.second; if (is_ff(ctx, ci)) { CellInfo *packed = create_ice_cell(ctx, "ICESTORM_LC", @@ -126,7 +127,7 @@ static void pack_carries(Context *ctx) std::unordered_set packed_cells; - for (auto cell : ctx->cells) { + for (auto cell : sorted(ctx->cells)) { CellInfo *ci = cell.second; if (is_carry(ctx, ci)) { packed_cells.insert(cell.first); @@ -201,7 +202,7 @@ static void pack_ram(Context *ctx) std::unordered_set packed_cells; std::vector new_cells; - for (auto cell : ctx->cells) { + for (auto cell : sorted(ctx->cells)) { CellInfo *ci = cell.second; if (is_ram(ctx, ci)) { CellInfo *packed = create_ice_cell(ctx, "ICESTORM_RAM", @@ -285,7 +286,7 @@ static void pack_constants(Context *ctx) bool gnd_used = false, vcc_used = false; - for (auto net : ctx->nets) { + for (auto net : sorted(ctx->nets)) { NetInfo *ni = net.second; if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) { @@ -329,7 +330,7 @@ static void pack_io(Context *ctx) log_info("Packing IOs..\n"); - for (auto cell : ctx->cells) { + for (auto cell : sorted(ctx->cells)) { CellInfo *ci = cell.second; if (is_nextpnr_iob(ctx, ci)) { CellInfo *sb = nullptr; @@ -412,8 +413,8 @@ static void promote_globals(Context *ctx) { log_info("Promoting globals..\n"); - std::unordered_map clock_count, reset_count, cen_count; - for (auto net : ctx->nets) { + std::map clock_count, reset_count, cen_count; + for (auto net : sorted(ctx->nets)) { NetInfo *ni = net.second; if (ni->driver.cell != nullptr && !is_global_net(ctx, ni)) { clock_count[net.first] = 0; -- cgit v1.2.3 From 7f368282700172925428e45f23b8b61e0bf39f94 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 22 Jun 2018 13:10:27 +0200 Subject: fixed namespace for gui section --- ice40/main.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'ice40') diff --git a/ice40/main.cc b/ice40/main.cc index 067637e8..9e925148 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -38,6 +38,8 @@ #include "timing.h" #include "version.h" +USING_NEXTPNR_NAMESPACE + void svg_dump_el(const GraphicElement &el) { float scale = 10.0, offset = 10.0; -- cgit v1.2.3