From 62b66e02085371c456dee95dc08d2cd41351c91f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Jul 2018 10:59:21 +0200 Subject: Rename getWireBelPin to getBelPinWire Signed-off-by: Clifford Wolf --- ice40/arch.cc | 2 +- ice40/arch.h | 2 +- ice40/arch_place.cc | 2 +- ice40/arch_pybindings.cc | 4 ++-- ice40/bitstream.cc | 6 +++--- ice40/main.cc | 20 ++++++++++---------- 6 files changed, 18 insertions(+), 18 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index 3833dcb7..a670f286 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -308,7 +308,7 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const return br; } -WireId Arch::getWireBelPin(BelId bel, PortPin pin) const +WireId Arch::getBelPinWire(BelId bel, PortPin pin) const { WireId ret; diff --git a/ice40/arch.h b/ice40/arch.h index 9a8ec7bc..566f807a 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -465,7 +465,7 @@ struct Arch : BaseCtx return chip_info->bel_data[bel.index].type; } - WireId getWireBelPin(BelId bel, PortPin pin) const; + WireId getBelPinWire(BelId bel, PortPin pin) const; BelPin getBelPinUphill(WireId wire) const { diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 116ab7d3..cf1276a7 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -110,7 +110,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const } else if (cell->type == id_sb_gb) { NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr); const NetInfo *net = cell->ports.at(id_glb_buf_out).net; - IdString glb_net = getWireName(getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT)); + IdString glb_net = getWireName(getBelPinWire(bel, PIN_GLOBAL_BUFFER_OUTPUT)); int glb_id = std::stoi(std::string("") + glb_net.str(this).back()); if (net->is_reset && net->is_enable) return false; diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc index fd5109b4..a1ce9f5b 100644 --- a/ice40/arch_pybindings.cc +++ b/ice40/arch_pybindings.cc @@ -82,8 +82,8 @@ void arch_wrap_python() fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getBelsAtSameTile"); - fn_wrapper_2a, - conv_from_str, conv_from_str>::def_wrap(ctx_cls, "getWireBelPin"); + fn_wrapper_2a, + conv_from_str, conv_from_str>::def_wrap(ctx_cls, "getBelPinWire"); fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getBelPinUphill"); fn_wrapper_1awire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) || - (ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] != IdString())) { + if ((ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_0).index] != IdString()) || + (ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_1).index] != IdString())) { input_en = true; } @@ -762,7 +762,7 @@ bool read_asc(Context *ctx, std::istream &in) if (cell.second->bel != BelId()) { for (auto &port : cell.second->ports) { PortPin pin = ctx->portPinFromId(port.first); - WireId wire = ctx->getWireBelPin(cell.second->bel, pin); + WireId wire = ctx->getBelPinWire(cell.second->bel, pin); if (wire != WireId()) { IdString name = ctx->getBoundWireNet(wire); if (name != IdString()) { diff --git a/ice40/main.cc b/ice40/main.cc index b84d6d92..24b49184 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -322,25 +322,25 @@ int main(int argc, char *argv[]) src_wires.push_back(w);*/ for (auto b : ctx->getBels()) { if (ctx->getBelType(b) == TYPE_ICESTORM_LC) { - src_wires.push_back(ctx->getWireBelPin(b, PIN_O)); + src_wires.push_back(ctx->getBelPinWire(b, PIN_O)); } if (ctx->getBelType(b) == TYPE_SB_IO) { - src_wires.push_back(ctx->getWireBelPin(b, PIN_D_IN_0)); + src_wires.push_back(ctx->getBelPinWire(b, PIN_D_IN_0)); } } for (auto b : ctx->getBels()) { if (ctx->getBelType(b) == TYPE_ICESTORM_LC) { - dst_wires.push_back(ctx->getWireBelPin(b, PIN_I0)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_I1)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_I2)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_I3)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_CEN)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_CIN)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_I0)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_I1)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_I2)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_I3)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_CEN)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_CIN)); } if (ctx->getBelType(b) == TYPE_SB_IO) { - dst_wires.push_back(ctx->getWireBelPin(b, PIN_D_OUT_0)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_OUTPUT_ENABLE)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_D_OUT_0)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_OUTPUT_ENABLE)); } } -- cgit v1.2.3